© 2018 Integrated Device Technology, Inc.

8

September 11, 2018

F1240 Datasheet

Electrical Characteristics

Table 6.

Electrical Characteristics

Parameter

Symbol

Condition

Minimum

Typical

Maximum

Units

Amplifier Switching Time [b]

50% control signal to 30dBc of

initial output power. STBY is

switched from logic HIGH to

Logic LOW.

100

ns

50% control signal to 0.5dBc

of final output power. STBY is

switched from logic LOW to

Logic HIGH.

200

Settling Time [b]

Any two Adjacent 1dB Steps

and settled to within +/-0.1dB

of the final power level

12

ns

Maximum Glitch

Only 1 transition has a glitch

greater than 0.4dB (8.5dB to

8.0dB)

0.4

1.5

dB

Clock to CSb Setup

CSb must be pulled low this

minimum interval BEFORE the next

rising clock edge

8

ns

Clock Pulse Width

Minimum clock interval from rising

to falling edge

20

ns

[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in

these columns that are not shown in bold italics are guaranteed by design characterization.

[b] Speeds are measured after SPI programming is completed (data latched with CSb = HIGH).