ADPA7004CHIP-SX datasheet(14/20 Pages) AD

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ADPA7004CHIPS

Data Sheet

Rev. 0 | Page 14 of 20

THEORY OF OPERATION

Figure 45 shows a simplified block diagram of ADPA7004CHIPS.

The ADPA7004CHIPS consists of two cascaded, four-stage

amplifiers, operating in quadrature between two 90° hybrids.

This balanced approach forms an amplifier with a combined

gain of 17 dB and a PSAT of 23.5 dBm. The 90° hybrids ensure

that the input and output return losses are excellent.

All gate bias voltages pads (VGG1234x) are internally connected

together. The drain bias pads (VDDxA through VDDxB) are

internally connected together in four pairs of two with each pair

providing bias current for one amplifier stage. In the case of the

gate bias, the gate bias voltage can be applied to a single pad.

However, in the case of the eight VDDxA and VDDxB drain bias

pad connections, all eight pads must be used to minimize

voltage drops. See Figure 46 and Figure 47 for further details on

biasing the various blocks.

A portion of the RF output signal (RFOUT) is directionally

coupled to a diode for detection of the RF output power. When

the diode is dc biased, the diode rectifies the RF power and

makes this power available for measurement as a dc voltage at

VDET. To allow temperature compensation of VDET, the reference

dc voltage detected through an identical diode that is not

coupled to the RF power is available on the VREF pad. The

difference of VREF − VDET provides a temperature compensated

detector voltage that is proportional to the RF output power

(see Figure 38 to Figure 42).

GND

RFIN

GND

VDD1A

VGG1234B VGG1234B VGG1234A VGG1234A

VDD1B

VDD2A

VDD2B

GND

RFOUT

GND

VREF

VDET

VDD3A

VDD3B

VDD4A

VDD4B

DRAIN BIAS VOLTAGES

TO INDIVIDUAL STAGES

GATE BIAS

VOLTAGE TO

ALL STAGES

DIRECTIONAL

COUPLER

90°COUPLER

FOUR-STAGE BALANCED AMPLIFIER

90°COUPLER

FOUR-STAGE BALANCED AMPLIFIER

ADPA7004CHIPS

Figure 45. Simplified Block Diagram

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