Interface Logic

RX

TX

Interface Logic

RX

TX

Interface Logic

RX

TX

Host

RX

TX

Figure 7-3. TMP144 Daisy-Chain: Bus Status During an Interrupt Request (Logic Low) From Second

Device

The interrupt on the bus is latched regardless of the status of LC. Writing a 1 to INT_EN automatically sets the

LC bit. The TMP144 holds the bus low until one of the following events happen:

• Global Interrupt Clear command is received.

• Global Software Reset command is received.

• A power-on reset event occurs.

Each of these events clears the INT_EN. The TMP144 does not issue future interrupts until the host writes sets

the INT_EN in the configuration register to re-enable future interrupts.

In a system with enabled interrupts, it is possible for a TMP144 on the bus to issue an interrupt at the same time

that the host starts a communication sequence. To avoid this scenario, TI recommends that the host should

check the status on the receiving side of the bus after transmitting the calibration byte. If it is 1, then the host can

continue with the communication. If it is 0, one of the TMP144 devices on the bus is issuing an alert and the host

must transmit a Global Interrupt Clear command.

TMP144

SBOS891A – OCTOBER 2018 – REVISED FEBRUARY 2021

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