Interface Logic

RX

TX

Interface Logic

RX

TX

Interface Logic

RX

TX

Host

RX

TX

Figure 7-10. TMP144 Daisy-Chain: Bus Status After First Device Address Assignment

After all devices on the chain have received the respective addresses, the host receives the last programmed

address on the chain + 1. The host can use this information to determine the total number of devices in the chain

and the respective address of each device.

After the initialization sequence, every device can be addressed individually or through global commands. This

global initialization sequence is a requirement and must be performed before any other communication.

7.5.4 Global Clear Interrupt

The host can initiate a global clear interrupt command (C[7:0] = 10101001) to all TMP144 devices in the daisy-

chain as shown in Figure 7-11. Upon receiving this command, the TMP144 disables future interrupts (bit-11 in

the Configuration Register is set to 0). If a TMP144 previously broke the bus connection and sent an interrupt

(logic low on the bus), the device now stops holding the bus low. The device sends the baud rate calibration

command and clear interrupt command to the next TMP144 in the chain, then reconnects the bus. In the case of

multiple devices having active interrupts, the clear interrupt command propagates through the daisy-chain,

disables all interrupts, and reconnects the bus across all devices.

GLBL

IN3/ID3

IN2/ID2

IN1/ID1

IN0/ID0

P1

P0

R/W

1

0

1

0

1

1

0

0

S

P

0

1

0

1

0

1

0

1

S

P

Calibration Byte (55h)

Command Byte

Figure 7-11. Global Clear Interrupt Command Flow

7.5.5 Global Read and Write

The host can initiate a global read or write command to all TMP144s in the daisy-chain by sending the read/write

command, consisting of C[7:3] = 11110 and C[2:1] to indicate the data register pointer P[1:0], as shown in Table

7-3. A global write command is indicated by C[0] = 0. The host must transfer at least one more byte of data for

the register, and every TMP144 in the daisy-chain updates the appropriate register as shown in Figure 7-12.

GLBL

IN3/ID3

IN2/ID2

IN1/ID1

IN0/ID0

P1

P0

R/W

0

1

1

1

1

0

P0

P1

S

P

0

1

0

1

0

1

0

1

S

P

Calibration Byte (55h)

Command Byte

D11

D12

D13

D14

D15

D8

D9

D10

S

P

D3

D4

D5

D6

D7

D0

D1

D2

S

P

Data Byte-1

Data Byte-2

Figure 7-12. Global Write Command Flow

TMP144

SBOS891A – OCTOBER 2018 – REVISED FEBRUARY 2021

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