AXM0F243 datasheet(32/53 Pages) ONSEMI

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AXM0F243

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(LIN), infrared interface (IrDA), and SmartCard (ISO7816)

protocols, all of which are minor variants of the basic UART

protocol. In addition, it supports the 9−bit multiprocessor

mode that allows addressing of peripherals connected over

common RX and TX lines. Common UART functions such

as parity error, break detect, and frame error are supported.

An 8−deep FIFO allows much greater CPU service latencies

to be tolerated.

SPI Mode: The SPI mode supports full Motorola SPI, TI

SSP (adds a start pulse used to synchronize SPI Codecs), and

National Microwire (half−duplex form of SPI). The SPI

block can use the FIFO.

GPIO

The AXM0F243 has up to 19 GPIOs. The GPIO block

implements the following:

• Eight drive modes:

♦ Analog input mode (input and output buffers

disabled)

♦ Input only

♦ Weak pull−up with strong pull−down

♦ Strong pull−up with weak pull−down

♦ Open drain with strong pull−down

♦ Open drain with strong pull−up

♦ Strong pull−up with strong pull−down

♦ Weak pull−up with weak pull−down

• Input threshold select (CMOS or LVTTL)

• Individual control of input and output buffer

enabling/disabling in addition to the drive strength

modes

• Selectable slew rates for dV/dt related noise control to

improve EMI

The pins are organized in logical entities called ports.

During power−on and reset, the blocks are forced to the

disable state so as not to crowbar any inputs and/or cause

excess turn−on current. A multiplexing network known as a

high−speed I/O matrix is used to multiplex between various

signals that may connect to an I/O pin.

Data output and pin state registers store, respectively, the

values to be driven on the pins and the states of the pins

themselves.

Every I/O pin can generate an interrupt if so enabled and

each I/O port has an interrupt request (IRQ) and interrupt

service routine (ISR) vector associated with it (5 for

AXM0F243).

Power

The power system has a voltage regulator in active mode

for the digital circuitry

The supply voltage range is 1.8 V to 3.6 V (unregulated

externally; internal regulator operational).

The AXM0F243 is powered by an external power supply

that can be anywhere in the range of 1.8 to 3.6 V. This range

is also designed for battery−powered operation. For

example, the chip can be powered from a battery system that

starts at 3.5 V and works down to 1.8 V

, the internal

regulator supplies the internal logic

Bypass capacitors must be used from VDDD to ground.

The typical practice for systems in this frequency range is to

use a capacitor in the 1−

mF range, in parallel with a smaller

capacitor (0.1

mF, for example). Note that these are simply

rules of thumb and that, for critical applications, the PCB

layout, lead inductance, and the bypass capacitor parasitic

should be simulated to design and obtain optimal bypassing.

AXM0F243 Datasheet(PDF) 32 Page - ON Semiconductor

AXM0F243 Datasheet(HTML) 32 Page - ON Semiconductor

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