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AS4LC2M8S1 Datasheet(PDF) 15 Page - Alliance Semiconductor Corporation

Part # AS4LC2M8S1
Description  3.3V 2M x 8/1M x 16 CMOS synchronous DRAM
PDF  28 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4LC2M8S1 Datasheet(HTML) 15 Page - Alliance Semiconductor Corporation

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AS4LC2M8S1
AS4LC1M16S1
7/5/00
ALLIANCE SEMICONDUCTOR
15
Mode register set command waveform
MRS can be issued only when both banks are idle.
Precharge waveforms
Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP. The earliest assertion of the precharge
command without losing any burst data is show below.
(normal write; BL = 4)
(normal read; BL = 4)
Auto precharge waveforms
A10 controls the selection of auto precharge during the read or write command cycle.
(write with auto precharge; BL = 4)
(read with auto precharge; BL = 4)
*The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be
issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
CLK
CMD
PRE
MRS
ACT
tRP
tRSC(min)
Or Auto Refresh
tMRD
CLK
CMD
DQ
WE
PRE
D0
D1
D2
D3
CLK
CMD
DQ(CL1)
DQ(CL2)
DQ(CL3)
Read data
PRE
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
CLK
CMD
DQ
WE
D0
D1
D2
D3
Auto precharge starts*
Auto precharge starts*
CLK
CMD
DQ(CL1)
DQ(CL2)
DQ(CL3)
Read data
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3



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