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AS4LC2M8S1 Datasheet(PDF) 21 Page - Alliance Semiconductor Corporation

Part # AS4LC2M8S1
Description  3.3V 2M x 8/1M x 16 CMOS synchronous DRAM
PDF  28 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4LC2M8S1 Datasheet(HTML) 21 Page - Alliance Semiconductor Corporation

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AS4LC2M8S1
AS4LC1M16S1
7/5/00
ALLIANCE SEMICONDUCTOR
21
Burst stop command waveform
read cycle
write cycle (BL = 8)
Precharge termination
A Precharge command terminates a burst read/write operation during the read cycle. The same bank can be activated after meeting tRP. If an
RD-burst is terminated, o/p will go to High Z after the number of cycles = CAS latency.
read cycle (CL = 1)
read cycle (CL = 2)
read cycle (CL = 3)
CLK
CMD
DQ (CL = 1)
DQ (CL = 2)
DQ (CL = 3)
Read data
Burst stop
Q0
Q1
Q2
Q0
Q1
Q2
Q0
Q1
Q2
tT
tOH
CLK
CMD
DQ
Burst stop
Write data
(CL = 1,2,3)
DQ
D1
D2
D3
CLK
CMD
DQ
Read data
PRE
Q0
Q1
Q2
Q3
tRP
ACT
CLK
CMD
DQ
Read data
Q0
Q1
Q2
PRE
ACT
Q3
tRP
tROH (CL = 2)
CLK
CMD
DQ
Read data
PRE
ACT
Q0
Q1
Q2
tROH (CL = 3)
Q3
tRP



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