ADRF5047

Data Sheet

Rev. 0 | Page 6 of 15

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

V1

RFC

GND

VSS

GND

GND

RF2

GND

RF3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

ADRF5047

TOP VIEW

(Not to Scale)

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE CONNECTED

TO RF AND DC GROUND OF THE PCB.

Figure 4. Pin Configuration (Top View)

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

V1

Control Input 1. See Table 5 for the control voltage truth table, and see Figure 6 for the interface

schematic.

2, 4, 7, 9, 10, 12 to 14, 16, 17, 19

GND

Ground. These pins must be connected to the RF and dc ground of the PCB.

3

RFC

RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking

capacitor is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface

schematic.

5

VSS

Negative Supply Voltage.

6

VDD

Positive Supply Voltage.

8

RF4

RF Throw Port 4. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor

is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.

11

RF3

RF Throw Port 3. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor

is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.

15

RF2

RF Throw Port 2. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor

is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.

18

RF1

RF Throw Port 1. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor

is required when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic.

20

V2

Control Input 2. See Table 5 for the control voltage truth table, and see Figure 6 for the interface

schematic.

EPAD

Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.

INTERFACE SCHEMATICS

RFC,

RF1,

RF2,

RF3,

RF4

Figure 5. RF Pins (RFC and RF1 to RF4) Interface Schematic

V1, V2

Figure 6. Control Pins (V1 and V2) Interface Schematic