MPC5554 datasheet(3/12 Pages) FREESCALE

3 / 12 page

Block Diagram

MPC5554 Microcontroller Product Brief, Rev. 2.1

Freescale Semiconductor

Block Diagram

Figure 1 shows a top-level block diagram of the MPC5554.

Figure 1. MPC5554 Block Diagram

Unified 32-Kbyte

Interrupt Controller

eQADC

FMPLL

Crossbar Switch (XBAR)

Peripheral Bridge B (PBRIDGE_B)

Peripheral Bridge A (PBRIDGE_A)

Master

Slave

Cache

Multiply

Unit

Load/Store Unit

Branch

Instruction

Unit

e200z6 Core

Nexus

LEGEND

JTAG

Exception

Handler

eTPU

channel

3K Data

RAM

16K Code

RAM

eMIOS

channel

Flash

2Mbyte

eDMA

channels

AMUX

ADCi

Slave

Nexus

Interface

External

Master

Interface

eTPU

channel

1.5V

Regulator

Control

System/Bus

Integration

Boot

Assist

Module

MPC5500 Device Module Acronyms

CAN

– Controller area network (FlexCAN)

DSPI

– Deserial/serial peripheral interface

DMA

– Enhanced direct memory access

eMIOS

– Enhanced modular I/O system

eQADC – Enhanced queued analog/digital converter

eSCI

– Enhanced serial communications interface

eTPU

– Enhanced time processing units

FMPLL – Frequency modulated phase-locked loop

SRAM

– Static RAM

e200z6 Core Component Acronyms

DEC

– Decrementer

FIT

– Fixed interval timer

– Time base

WDT

– Watchdog timer

Prediction Unit

Signal

Processing

Engine

64-bit General

Purpose

Registers

Special

Purpose

Registers

Integer

Execution

Unit

SRAM

64 Kbyte

Memory

Management

Unit

Core Timers

Unit

(FIT, TB, DEC)

MPC5554 Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

MPC5554 Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL