MPC5554 Microcontroller Product Brief, Rev. 2.1

Features

Freescale Semiconductor

6

— Bus monitor

— Chip selects: 4 chip select (CS[0:3]) signals

— Configurable wait states

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System integration unit (SIU)

— Centralized GPIO control of 214 I/O and bus pins

— Centralized pad control on a per-pin basis

— System reset monitoring and generation

— External interrupt inputs, filtering, and control

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Error correction status module (ECSM)

— Configurable error-correcting codes (ECC) reporting for internal SRAM and Flash memories

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On-chip Flash

— 2 Mbytes burst Flash memory

— 256K

× 64 bit configuration

— Censorship protection scheme to prevent Flash content visibility

— Hardware read-while-write feature that allows blocks to be erased/programmed while other

blocks are being read (used for EEPROM emulation and data calibration)

— 20 blocks, ranging from 16 Kbytes to 128 Kbytes, to support features such as boot block,

operating system block, and EEPROM emulation

— Read while write with multiple partitions

— Parallel programming mode to support rapid end of line programming

— Hardware programming state machine

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Configurable cache memory, 32-Kbyte

— 8-way set-associative, unified (instruction and data) cache

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On-chip, internal static RAM (SRAM)

— 64-Kbyte general-purpose RAM; 32 Kbytes on standby power

— ECC performs single bit correction, double bit error detection

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Boot assist module (BAM)

— Enables and manages the transition of MCU from reset to user code execution in the

following configurations:

– User application can boot from internal or external Flash memory

– Download and execution of code via FlexCAN or eSCI

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Enhanced modular I/O system (eMIOS)

— 24 orthogonal channels with double action, PWM, and modulus counter functionality

— Supports all DASM and PWM modes of MIOS14 (MPC5xx)

— 4 selectable time bases plus shared time or angle counter bus

— DMA and interrupt request support