MPC5554 Microcontroller Product Brief, Rev. 2.1

Features

Freescale Semiconductor

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2

Features

This section provides a high-level description of the major features of the MPC5554.

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High performance e200z6 core processor

— 32-bit PowerPC Book E compliant CPU

— 32 64-bit general-purpose registers (GPRs)

— Memory management unit (MMU) with 32-entry, fully-associative translation look-aside

buffer (TLB)

— Branch processing unit

— Fully pipelined load/store unit

— 32-Kbyte unified cache with line locking

– 8-way set associative

– 2 32-bit fetches per clock

– 8-entry store buffer

– Way locking

– Supports assigning cache as instruction or data only on a per way basis

– Supports tag and data parity

— Vectored interrupt support

— Interrupt latency < 70 ns @132MHz (measured from interrupt request to execution of first

instruction of interrupt exception handler)

— Reservation instructions for implementing read-modify-write constructs (internal SRAM and

Flash)

— Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit GPRs

— Floating point

–IEEE

® 754 compatible with software wrapper

– Single precision in hardware and double precision with software library

– Conversion instructions between single precision floating point and fixed point

— Long cycle time instructions, except for guarded loads, do not increase interrupt latency in the

MPC5554. To reduce latency, long cycle time instructions are aborted upon interrupt requests.

— Extensive system development support through Nexus debug module

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Crossbar switch (XBAR)

— 3 master ports; 5 slave ports

— 32-bit address bus; 64-bit data bus

— Simultaneous accesses from different masters to different slaves (there is no clock penalty

when a parked master accesses a slave)