MCP47FVB28T-MQ datasheet(94/124 Pages) MICROCHIP

94 / 124 page

MCP47FXBX4/8

DS20006368A-page 94

 2020 Microchip Technology Inc.

The second Start bit is sent to address the rare

possibility of an erroneous write. This could occur if the

master device was reset while sending a WRITE com-

mand to the MCP47FXBX4/8, and then as the master

device returns to normal operation and issues a Start

condition, while the MCP47FXBX4/8 devices issue an

acknowledge. In this case, if the second Start bit is not

sent (and the Stop bit was sent) the MCP47FXBX4/8

could initiate a write cycle.

The Stop bit terminates the current I2C bus activity. The

MCP47FXBX4/8 waits to detect the next Start

condition.

This sequence does not affect any other I2C devices

which may be on the bus, as they should disregard this

for being an invalid command.

8.2

Power Supply Considerations

The power source should be as clean as possible. The

power supply to the device is also used for the DAC

voltage reference internally if the internal VDD is

selected as the resistor ladder’s reference voltage

(VRnB:VRnA = ‘00’).

Any noise induced on the VDD line can affect the DAC

performance. Typical applications will require a bypass

capacitor in order to filter out high-frequency noise on

the VDD line. The noise can be induced onto the power

supply’s traces or as a result of changes on the DAC out-

put. The bypass capacitor helps to minimize the effect of

these noise sources on signal integrity. Figure 8-3

shows an example of using two bypass capacitors (a

10 µF tantalum capacitor and a 0.1 µF ceramic capaci-

tor) in parallel on the VDD line. These capacitors should

be placed as close to the VDD pin as possible (within

4 mm). If the application circuit has separate digital and

analog power supplies, the VDD and VSS pins of the

device should reside on the analog plane.

When setting the part voltage reference to Band Gap

mode, the use of the VREF pin decoupling capacitors is

not recommended.

FIGURE 8-3:

Circuit Example.

Note:

The potential for this erroneous write

ONLY occurs if the master device is reset

while sending a WRITE command to the

MCP47FEBXX.

Analog

VDD

SDA

SCL

VSS

VOUT0

To MCU

R1 and R2 are I2C pull-up resistors:

R1 and R2:

 - 10 k for fSCL = 100 kHz to 400 kHz

~700

 for fSCL = 3.4 MHz

C1:

0.1 µF capacitor

= Ceramic

C2:

10 µF capacitor

= Tantalum

C3:

~ 0.1 µF

= Optional to reduce noise

in VOUT pin

C4:

0.1 µF capacitor

= Ceramic

C5:

10 µF capacitor

= Tantalum

C6:

0.1 µF capacitor

= Ceramic

Optional

(a) Circuit when VDD is selected as reference.

(Note: VDD is connected to the reference circuit internally.)

(b) Circuit when external reference is used.

Output

VREF

LAT/HVC

VOUTN

Analog

VDD

SDA

SCL

To MCU

VREF

Analog

VSS

VOUT0

Optional

Output

LAT/HVC

VOUTN

MCP47FVB28T-MQ Datasheet(PDF) 94 Page - Microchip Technology

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