CDCE906 datasheet(7/33 Pages) TI

7 / 33 page

www.ti.com

CDCE906

SCAS814 – NOVEMBER 2005

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

LVCMOS PARAMETER FOR Vccout = 3.3-V Mode

Vccout = 3 V, IOH = –0.1 mA

2.9

VOH

LVCMOS high-level output voltage

Vccout = 3 V, IOH = –4 mA

2.4

Vccout = 3 V, IOH = –6 mA

2.1

Vccout = 3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

Vccout = 3 V, IOL = 4 mA

0.5

Vccout = 3 V, IOL = 6 mA

0.85

All PLL bypass

tPLH,

Propagation delay

tPHL

VCO bypass

tr0/tf0

Rise and fall time for output slew rate 0

Vccout = 3.3 V (20%–80%)

3.3

tr1/tf1

Rise and fall time for output slew rate 1

Vccout = 3.3 V (20%–80%)

2.5

tr2/tf2

Rise and fall time for output slew rate 2

Vccout = 3.3 V (20%–80%)

1.6

tr3/tf3

Rise and fall time for output slew rate 3

Vccout = 3.3 V (20%–80%)

0.6

1 PLL, 1 Output

TBD

tjit(cc)

Cycle-to-cycle jitter (4)(5)

3 PLLs, 3 Outputs

120

TBD

1 PLL, 1 Output

TBD

tjit(per)

Peak-to-peak period jitter(5)

3 PLLs, 3 Outputs

130

TBD

Output skew (see (6) and Table 5)

1.6-ns rise/fall time (default) at

tsk(o)

200

fvco = 150 MHz, Pdiv = 3

fvco = 250 MHz, Pdiv = 1

odc

Output duty cycle(7)

45%

55%

fvco = 250 MHz, Pdiv = 25

LVCMOS PARAMETER FOR Vccout = 2.5-V Mode

Vccout = 2.3 V, IOH = 0.1 mA

2.2

VOH

LVCMOS high-level output voltage

Vccout = 2.3 V, IOH = –3 mA

1.7

Vccout = 2.3 V, IOH = –4 mA

1.5

Vccout = 2.3 V, IOL = 0.1 mA

0.1

VOL

LVCMOS low-level output voltage

Vccout = 2.3 V, IOL = 3 mA

0.5

Vccout = 2.3 V, IOL = 4 mA

0.85

All PLL bypass

tPLH,

Propagation delay

tPHL

VCO Bypass

Rise and fall time for output

tr0/tf0

Vccout = 2.5 V (20%–80%)

3.9

slew rate 0

Rise and fall time for output

tr1/tf1

Vccout = 2.5 V (20%–80%)

2.9

slew rate 1

Rise and fall time for output

tr2/tf2

Vccout = 2.5 V (20%–80%)

2.0

slew rate 2

Rise and fall time for output

tr3/tf3

Vccout = 2.5 V (20%–80%)

0.8

slew rate 3

Cycle-to-cycle jitter (4)(5)

1 PLL, 1 Output

TBD

tjit(cc)

3 PLLs, 3 Outputs

130

TBD

Peak-to-peak period jitter(5)

1 PLL, 1 Output

TBD

tjit(per)

3 PLLs, 3 Outputs

140

TBD

Output skew (see (6) and Table 5)

2-ns rise/fall time (default) at

tsk(o)

250

fvco = 150 MHz, Pdiv = 3

(4)

50000 cycles

(5)

Jitter depends on configuration.

(6)

The tsk(o) specification is only valid for equal loading of all outputs.

(7)

odc depends on output rise and fall time (tr/tf); above limits are for normal tr/tf.

CDCE906 Datasheet(PDF) 7 Page - Texas Instruments

CDCE906 Datasheet(HTML) 7 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Datasheet Download

Link URL