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XO

or

2LVCMOS

or

Differential

input

CLK_IN0

CLK_IN1

XO

or

2LVCMOS

or

Differential

input

CLK_IN0

CLK_IN1

Input source select

(from EEPROM)

PLL Configuration and Setting

CDCE906

SCAS814 – NOVEMBER 2005

For example, if a 27-MHz crystal with ESR of 50

Ω is used and 2 × C

level should be held to a minimum to avoid over driving the crystal. The maximum power dissipation is specified

for each type of crystal in the oscillator specifications, i.e., 100

µW for the example above.

Single-Ended LVCMOS Clock Inputs

When selecting the LVCMOS clock mode, CLK_IN0 and CLK_IN1 act as regular clock inputs pins and can be

driven up to 200 MHz. Both clock inputs circuitry are equal in design and can be used independently to each

other (see Figure 12). The internal clock select bit, Byte 10, Bit [4], selects one of the two input clocks. CLK_IN0

is the default selection. There is also the option to program the external control pin S0/A0/CLK_SEL as clock

select pin, Byte 10, Bit [1:0].

The two clock inputs can be used for redundancy switching, i.e. to switch between a primary clock and

secondary clock. Note a phase difference between the clock inputs may require PLL correction. Also in case of

different frequencies between the primary and secondary clock, the PLL has to re-lock to the new frequency.

A.

CLK_SEL is optional and can be configured by EEPROM setting.

Figure 12. LVCMOS Clock Input Circuitry

Differential Clock Inputs

The CDCE906 supports differential signaling as well. In this mode, CLK_IN0 and CLK_IN1 pin serve as

differential signal inputs and can be driven up to 200 MHz.

The minimum magnitude of the differential input voltage is 400mV over a differential common-mode input voltage

recommended to adjust the different physical layers (see Figure 13). The capacitor removes the dc component of

the signal (common-mode voltage), while the ac component (voltage swing) is passed on. A resistor pull-up

and/or pull-down network represents the biasing structure used to set the common-mode voltage on the receiver

side of the ac-coupling capacitor.

Figure 13. Differential Clock Input Circuitry

The CDCE906 includes three PLLs which are equal in function and performance. Except PLL2 which in addition

supports spread spectrum clocking (SSC) generation. Figure 14 shows the block diagram of the PLL.

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