LTC2430IGN datasheet(23/40 Pages) LINER

23 / 40 page

LTC2430/LTC2431

24301f

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 12. The CPAR capacitor

includes the LTC2430/LTC2431 pin capacitance (5pF typi-

cal) plus the capacitance of the test fixture used to obtain

the results shown in Figures 13 and 14. A careful imple-

mentation can bring the total input capacitance (CIN +

CPAR) closer to 5pF thus achieving better performance

than the one predicted by Figures 13 and 14. For simplic-

ity, two distinct situations can be considered.

For relatively small values of input capacitance (CIN <

0.01

µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

source impedance result in only small errors. Such values

for CIN will deteriorate the converter offset and gain

performance without significant benefits of signal filter-

ing and the user is advised to avoid them. Nevertheless,

when small values of CIN are unavoidably present as

parasitics of input multiplexers, wires, connectors or

sensors, the LTC2430 or LTC2431 can maintain its excep-

tional accuracy while operating with relative large values

of source resistance as shown in Figures 13 and 14. These

measured results may be slightly different from the first

order approximation suggested earlier because they in-

clude the effect of the actual second order input network

together with the nonlinear settling process of the input

amplifiers. For small CIN values, the settling on IN+ and

IN– occurs almost independently and there is little benefit

in trying to match the source impedance for the two pins.

Larger values of input capacitors (CIN > 0.01µF) may be

required in certain configurations for antialiasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

When FO = LOW (internal oscillator and 60Hz notch), the

typical differential input resistance is 21.6M

Ω which will

generate a gain error of approximately 0.023ppm for each

ohm of source resistance driving IN+ or IN–. When FO =

HIGH (internal oscillator and 50Hz notch), the typical

differential input resistance is 26M

Ω which will generate

a gain error of approximately 0.019ppm for each ohm of

source resistance driving IN+ or IN–. When FO is driven by

an external oscillator with a frequency fEOSC (external

conversion clock operation), the typical differential input

resistance is 3.3 • 1012/fEOSCΩ and each ohm of source

resistance driving IN+ or IN– will result in 0.15 • 10–6 •

fEOSCppm gain error. The effect of the source resistance on

the two input pins is additive with respect to this gain error.

APPLICATIO S I FOR ATIO

Figure 12. An RC Network at IN+ and IN–

Figure 13. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)

Figure 14. –FS Error vs RSOURCE at IN

+ or IN– (Small CIN)

CIN

2431 F12

VINCM + 0.5VIN

RSOURCE

CPAR

≅20pF

CIN

VINCM – 0.5VIN

RSOURCE

CPAR

≅20pF

IN+

IN –

LTC2430/

LTC2431

RSOURCE (Ω)

100

10k

100k

2431 F13

–10

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 3.75V

VIN– = 1.25V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0pF

CIN = 0.001µF

CIN = 100pF

RSOURCE (Ω)

–50

–40

–30

–20

–10

100

10k

2431 F14

100k

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 1.25V

VIN– = 3.75V

FO = GND

TA = 25°C

CIN = 0.01µF

CIN = 0pF

CIN = 0.001µF

CIN = 100pF

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