LTC2430IGN datasheet(26/40 Pages) LINER

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LTC2430/LTC2431

24301f

into about 0.11ppm additional INL error. When FO = HIGH

(internal oscillator and 50Hz notch), every 100

Ωof source

resistance driving REF+ or REF– translates into about

0.092ppm additional INL error. When FO is driven by an

external oscillator with a frequency fEOSC, every 100Ω of

source resistance driving REF+ or REF– translates into

about 0.73 • 10–6 • fEOSCppm additional INL error. Fig-

ure 19 shows the typical INL error due to the source

resistance driving the REF+ or REF– pins when large CREF

values are used. The effect of the source resistance on the

two reference pins is additive with respect to this INL error.

In general, matching of source impedance for the REF+

APPLICATIO S I FOR ATIO

and REF– pins does not help the gain or the INL error. The

user is thus advised to minimize the combined source

impedance driving the REF+ and REF– pins rather than to

try to match it.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typical better than

1%. Such a specification can also be easily achieved by an

external clock. When relatively stable resistors (50ppm/

°C)

are used for the external source impedance seen by REF+

and REF–, the expected drift of the dynamic current gain

error will be insignificant (about 1% of its value over the

entire temperature and voltage range). Even for the most

stringent applications, a one-time calibration operation

may be sufficient.

In addition to the reference sampling charge, the reference

pins ESD protection diodes have a temperature dependent

leakage current. This leakage current, nominally 1nA

(

±10nA max), results in a small gain error. A 100Ω source

resistance will create a 0.05

µV typical and 0.5µV maxi-

mum full-scale error.

Figure 18a. +FS Error vs RSOURCE at REF

+ or REF– (Large CREF)

Figure 18b. – FS Error vs RSOURCE at REF+ or REF– (Large CREF)

RSOURCE (Ω)

–50

–60

–30

–10

–40

–20

200

400

600

800

2431 F18a

1000

100

300

500

700

900

CREF = 1µF, 10µF

CREF = 0.1µF

CREF = 0.01µF

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 3.75V

VIN– = 1.25V

FO = GND

TA = 25°C

RSOURCE (Ω)

200

400

600

800

2431 F18b

1000

100

300

500

700

900

CREF = 1µF, 10µF

CREF = 0.1µF

CREF = 0.01µF

VCC = 5V

VREF+ = 5V

VREF– = GND

VIN+ = 1.25V

VIN– = 3.75V

FO = GND

TA = 25°C

Figure 19. INL vs Differential Input Voltage (VIN = IN+ – IN–)

and Reference Source Resistance (RSOURCE at REF+ and REF–)

for Large CREF Values (CREF ≥ 1µF)

VINDIF/VREFDIF

–0.5

0.3

2431 F19

–3

–9

–6

–12

–15

–0.3

–0.4

–0.1

–0.2

0.1 0.2

0.4

0.5

RSOURCE = 1k

RSOURCE = 10k

RSOURCE = 5k

VCC = 5V

VREF+ = 5V

VREF– = GND

VINCM = 0.5(VIN

+ + V

–) = 2.5V

FO = GND

CREF = 10µF

TA = 25°C

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