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STM32H723VG Datasheet(PDF) 193 Page - STMicroelectronics

Part # STM32H723VG
Description  32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
PDF  227 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H723VG Datasheet(HTML) 193 Page - STMicroelectronics

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DS13313 Rev 2
193/227
STM32H723xE/G
Electrical characteristics
208
Figure 48. SPI timing diagram - slave mode and CPHA = 0
tsu(MI)
Data input setup time
Master mode
2.5
-
-
ns
tsu(SI)
Slave mode
1
-
-
th(MI)
Data input hold time
Master mode
3
-
-
th(SI)
Slave mode
1.5
-
-
ta(SO)
Data output access time
Slave mode
9
13
27
tdis(SO)
Data output disable time
Slave mode
0
1
5
tv(SO)
Data output valid time
Slave mode,
2.7 V < VDD < 3.6 V
-7.5
11
Slave mode,
1.62 V < VDD < 3.6 V
-
7.5
12/16(4)
tv(MO)
Master mode,
1.62 V < VDD < 3.6 V
-
1
1.5/5.5(6)
th(SO)
Data output hold time
Slave mode
7
-
-
th(MO)
Master mode
0.5
-
-
1. Guaranteed by characterization results.
2. The values given in the above table might be degraded when PC3_C/PC2_C I/Os are used (not available on all packages).
3. This value is obtained by using PA9 or PA12 I/O.
4. This value is obtained by using PC2 or PJ11 I/O.
5. tSCK = tker_ck * baud rate prescaler.
6. This value is obtained by using PC3 or PJ10 I/O.
Table 107. SPI characteristics(1)(2) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MSv41658V1
NSS input
CPHA=0
CPOL=0
CPHA=0
CPOL=1
MISO output
MOSI input
tsu(SI)
th(SI)
tw(SCKL)
tw(SCKH)
tc(SCK)
tr(SCK)
th(NSS)
tdis(SO)
tsu(NSS)
ta(SO)
tv(SO)
Next bits IN
Last bit OUT
First bit IN
First bit OUT
Next bits OUT
th(SO)
tf(SCK)
Last bit IN



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