R
EM6521
Copyright © 2005, EM Microelectronic-Marin SA
19
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6.4.2 Pull-up or Pull-down
On each terminal of PB[3:0] an internal input pull-up (metal mask MPBPU[n]) or pull-down (metal mask
MPBPD[n]) resistor can be connected per metal mask option (ROM version only). Per default the two resistors
are in place. In this case one can chose per software to have either a pull-up, a pull-down or no resistor. See
below.
For Metal mask selection and available resistor values refer to chapter
116H
0.
Pull-down ON : MPBPD[n] must be in place ,
AND bit NoPdPB[n] must be ‘0’ .
Pull-down OFF: MPBPD[n] is not in place,
OR if MPBPD[n] is in place NoPdPB[n] = ‘1’ cuts off the pull-down.
OR selecting NchOpDPB[n] = ‘1’ cuts off the pull-down.
Pull-up ON *
: MPBPU[n] must be in place,
AND bit NchOpDPB[n] must be ‘1’ ,
AND (bit PBIOCntl[n] = ‘0’ (input mode) OR if PBIOCntl[n] = ‘1’ while PBData[n] = 1. )
Pull-up OFF* : MPBPU[n] is not in place,
OR if MPBPU[n] is in place NchOpDPB[n] = ‘0’ cuts off the pull-up,
OR if MPBPU[n] is in place and if NchOpDPB[n] = ‘1’ then PBData[n] = 0 cuts off the pull-up.
Never pull-up and pull-down can be active at the same time.
For POWER SAVING one can switch off the port B pull resistors between two read phases. No cross current
flows in the input amplifier while the port B is not read. The recommended order is :
• Switch on the pull resistor.
• Allow sufficient time - RC constant - for the pull resistor to drive the line to either V
SS
or VDD.
• Read the port B
• Switch off the pull resistor
Minimum time with current on the pull resistor is 4 system clock periods, if the RC time constant is lower than 1
system clock period. Adding a NOP instruction before reading moves the number of periods with current in the
pull resistor to 6 and the maximum RC delay to 3 clock periods.
6.4.3 CMOS / NCH. Open Drain Output
The port B outputs can be configured as either CMOS or Nch. open drain outputs. In CMOS both logic ‘1’ and
‘0’ are driven out on the terminal. In Nch. Open Drain only the logic ‘0’ is driven on the terminal, the logic ‘1’
value is defined by the internal pull-up resistor (if implemented), or high impedance.
Figure 12. CMOS or Nch. Open Drain Outputs
I / O
Te rm in a l
PB [n ]
MU X
A c tiv e P u llu p
for H igh S tate
DR [n ]
F reque nc y
O u tputs
T ri-S tate O utp ut
B uffer : H igh
Im pedan c e for
Da ta = 1
I / O
Te rm in a l
PB [n ]
MU X
DR [n ]
F reque nc y
O utputs
T ri-S tate O utp ut
B uffer : c lo s ed
Da ta
1
C M OS Ou tp u t
N c h. O p en D ra in O utp ut
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