MCP6006 datasheet(17/46 Pages) MICROCHIP

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DS20006411B-page 17

MCP6006/6R/6U/7/9

4.4

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. While a unity gain buffer (G = +1 V/V) is the

most sensitive to the capacitive loads, all gains show

the same general behavior.

When driving large capacitive loads with the

MCP6006/6R/6U/7/9 op amp, a small series resistor at

the output (RISO in Figure 4-6) improves the feedback

loop’s phase margin (stability) by making the output

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitance load.

FIGURE 4-6:

Output Resistor, RISO,

Stabilizes Large Capacitive Loads.

4.5

Supply Bypass

The MCP6006/6R/6U/7/9 op amp’s power supply pin

(VDD for single-supply) should have a local bypass

capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good

high-frequency performance. It can use a bulk capaci-

tor (i.e., 1 µF or larger) within 100 mm to provide large,

slow currents. This bulk capacitor can be shared with

other analog parts.

4.6

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6006/6R/6U/7/9’s bias current at +25°C (±1 pA,

typical).

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-7.

FIGURE 4-7:

Example Guard Ring Layout

for Inverting Gain.

Noninverting Gain and Unity Gain Buffer:

a) Connect the noninverting pin (VIN+) to the

input with a wire that does not touch the

PCB surface.

b) Connect the guard ring to the inverting input

pin (VIN-). This biases the guard ring to the

Common-mode input voltage.

Inverting Gain and Transimpedance Gain

Amplifiers (convert current to voltage, such as

photo detectors):

a) Connect the guard ring to the noninverting

input pin (VIN+). This biases the guard ring

to the same reference voltage as the

op amp (e.g., VDD/2 or ground).

b) Connect the inverting pin (VIN-) to the input

with a wire that does not touch the PCB

surface.

4.7

Unused Op Amps

An unused op amp in a dual (MCP6007) or quad

(MCP6009) package should be configured as shown in

Figure 4-8. These circuits prevent the output from

toggling and causing crosstalk. Circuit A sets the

op amp at its minimum noise gain. The resistor divider

produces any desired reference voltage within the out-

put voltage range of the op amp; the op amp buffers

that reference voltage. Circuit B uses the minimum

number of components.

FIGURE 4-8:

Unused Op Amps.

VIN

RISO

VOUT

–

MCP6006

Guard Ring

VIN-VIN+

VSS

¼ MCP6009 (A)

¼ MCP6009 (B)

REF



VREF

VDD

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