M69KB096AA datasheet(15/48 Pages) STMICROELECTRONICS

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M69KB096AA

Bus Configuration Register

The Bus Configuration Register (BCR) defines

how the PSRAM interacts with the system memory

bus. Overall, it is identical to its counterpart on

burst mode Flash devices.

At power-up, BCR is initialized to 9D4Fh.

Refer to Table 5. for the description of the Bus

Configuration Register Bits.

Operating Mode Bit (BCR15). The

Operating

Mode bit allows the Synchronous Burst mode or

the Asynchronous mode (default setting) to be se-

lected.

Latency Counter Bits (BCR13-BCR11). The

Latency Counter bits are used to set the number of

clock cycles between the beginning of a Read or

Write operation and the first data becoming avail-

able. For correct operation, the number of clock

cycles can only be equal to 3 or 4 (default settings)

and the Latency Counter bits can only assume the

values shown in Table 5., Bus Configuration Reg-

ister

Definition.

See

also

Table

7., Latency

Counter Configuration, and Figure 12., Example

of Latency Counter Configuration).

WAIT Polarity Bit (BCR10). The WAIT Polarity

bit indicates whether the WAIT output signal is ac-

tive High or Low. As a consequence, it also deter-

mines whether the WAIT signal requires a pull-up

or pull-down resistor to maintain the de-asserted

state.

By default, the WAIT output signal is active High.

WAIT Configuration Bit (BCR8). The

system

memory controller uses the WAIT signal to control

data transfer during Synchronous Burst Read

Read and Write operations.

The WAIT Configuration bit is used to determine

when the transition of the WAIT output signal be-

tween the asserted and the deasserted state oc-

curs with respect to valid data available on the

data bus.

When the Wait Configuration bit is set to ‘0’, data

is valid or invalid on the first Clock rising edge im-

mediately after the WAIT signal transition to the

deasserted or asserted state.

When the Wait Configuration bit is set to ‘1’ (de-

fault settings), the WAIT signal transition occurs

one clock cycle prior to the data bus going valid or

invalid.

See Figure 10., WAIT Configuration Example, and

Figure 11., Example of WAIT Configuration During

Synchronous Burst Operation.

Clock Configuration Bit (BCR6). The

Clock

Configuration bit is used to configure the activ-

eedge of the Clock signal, K, during Synchronous

Burst Read or Write operations. When the Clock

Configuration bit is set to ’1’ (default setting), the

rising edge of the Clock is active. Configuring the

active clock edge to the falling edge (BCR6 set to

‘0’) is not supported.

All of the waveforms shown in this datasheet cor-

respond to a Clock signal active on the rising

edge.

Driver Strength Bit (BCR5). The Driver Strength

bit allows to set the output drive strength to adjust

to different data bus loading. Normal driver

strength (full drive) and reduced driver strength (a

quarter drive) are available.

By default, outputs are configured at ‘half drive”

strength.

Burst Wrap Bit (BCR3). The burst reads can be

confined inside the 4, 8 or 16 Word boundary

(wrap) or allowed to step across the boundary (no

wrap). The Burst Wrap bit is used to select be-

tween ‘wrap’ and ‘no wrap’. If the Burst Wrap bit is

set to ‘1’ (no wrap), the device outputs data se-

quentially regardless of burst boundaries. When

Continuous Burst operation is selected, the inter-

nal address switches to 000000h if the read ad-

dress passes the last address. By default, Burst

wrap is selected.

See also Table 6., Burst Type Definition.

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