M69KB096AA

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Figure 33. Configuration Register Write in Synchronous Mode Followed by Read Operation

Note: 1. Non default BCR Register settings: Latency code two (three clocks); WAIT active Low; Hold data one clock; WAIT asserted during

delay.

Latch Control Register Address

Hi-Z

OPCODE

ADDRESS

ADDRESS

Hi-Z

Latch Control Register Value

AI06779b

A0-A21

except A19

K

A19

CR

E

G

W

DQ0-DQ15

LB/UB

tAVKH

L

WAIT

tCHKH

tKHLH

tELKH

tEHEL

tWLKH

tKHLH

tELTV

tRHKH

tKHRL