PCIMX6D4AVT12AD datasheet(37/170 Pages) NXP

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Electrical Characteristics

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018

NXP Semiconductors

4.4.5

MLB PLL

The MediaLB PLL is necessary in the MediaLB 6-Pin implementation to phase align the internal and

external clock edges, effectively tuning out the delay of the differential clock receiver and is also

responsible for generating the higher speed internal clock, when the internal-to-external clock ratio is

not 1:1.

4.4.6

Arm PLL

4.5

On-Chip Oscillators

4.5.1

OSC24M

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT.

The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight

forward biased-inverter implementation is used.

4.5.2

OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements a low power oscillator. It also implements a power mux such that it can be powered

from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes

power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when

VDD_HIGH_IN is lost.

In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz

clock will automatically switch to the internal ring oscillator.

Table 18. MLB PLL Electrical Parameters

Parameter

Value

Lock time

<1.5 ms

Table 19. Arm PLL Electrical Parameters

Parameter

Value

Clock output range

650 MHz~1.3 GHz

Reference clock

24 MHz

Lock time

<2250 reference cycles

PCIMX6D4AVT12AD Datasheet(PDF) 37 Page - NXP Semiconductors

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