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PCIMX6D4AVT12AD Datasheet(PDF) 41 Page - NXP Semiconductors |
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PCIMX6D4AVT12AD Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 170 page  Electrical Characteristics i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 6, 11/2018 NXP Semiconductors 41 4.6.4.1 LPDDR2 Mode I/O DC Parameters For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” The parameters in Table 24 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Table 23. RGMII I/O 2.5V I/O DC Electrical Parameters1 1 Input Mode Selection: SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 10 (1.8V Mode) SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 11 (2.5V Mode). Parameter Symbol Test Conditions Min Max Units High-level output voltage1 VOH Ioh= -0.1 mA (DSE=001,010) Ioh= -1.0 mA (DSE=011,100,101,110,111) OVDD-0.15 —V Low-level output voltage1 VOL Iol= 0.1 mA (DSE=001,010) Iol= 1.0 mA (DSE=011,100,101,110,111) —0.15 V Input Reference Voltage Vref — 0.49xOVDD 0.51xOVDD V High-Level input voltage 2, 3 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s. VIH — 0.7xOVDD OVDD V Low-Level input voltage 2, 3 VIL —0 0.3xOVDD V Input Hysteresis(OVDD=1.8V) VHYS_HighVDD OVDD=1.8V 250 — mV Input Hysteresis(OVDD=2.5V) VHYS_HighVDD OVDD=2.5V 250 — mV Schmitt trigger VT+ 3, 4 4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled (register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0). VTH+ —0.5xOVDD — mV Schmitt trigger VT- 3, 4 VTH- — — 0.5xOVDD mV Pull-up resistor (22 k Ω PU) RPU_22K Vin=0V — 212 μA Pull-up resistor (22 k Ω PU) RPU_22K Vin=OVDD — 1 μA Pull-up resistor (47 k Ω PU) RPU_47K Vin=0V — 100 μA Pull-up resistor (47 k Ω PU) RPU_47K Vin=OVDD — 1 μA Pull-up resistor (100 k Ω PU) RPU_100K Vin=0V — 48 μA Pull-up resistor (100 k Ω PU) RPU_100K Vin=OVDD — 1 μA Pull-down resistor (100 k Ω PD) RPD_100K Vin=OVDD — 48 μA Pull-down resistor (100 k Ω PD) RPD_100K Vin=0V — 1 μA Keeper Circuit Resistance Rkeep — 105 165 k Ω Input current (no pull-up/down) Iin VI = 0,VI = OVDD -2.9 2.9 μA |
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