IMX7ULPCECB2 datasheet(22/122 Pages) NXP

22 / 122 page

Table 1. i.MX 7ULP modules list (continued)

Block Name

Block Mnemonic

Subsystem

Power

Domain

Brief description

or refreshing the WDOG. If this periodic

refreshing does not occur, the WDOG

resets the system. WDOG0 is in the real-

time domain. WDOG1 and WDOG2 are

in the application domain.

XRDC Manager

MGR

Multicore Peripherals

and Resource Domain

Control submodules

The XRDC Manager (MGR) submodule

coordinates all programming model

reads and writes.

XRDC Master Domain

Assignment Controller

MDAC

Multicore Peripherals

and Resource Domain

Control submodules

AD, RT

The XRDC Master Domain Assignment

Controller (MDAC) submodule handles

resource assignments and generation of

the domain identifiers.

XRDC Memory

Region Controller

MRC

Multicore Peripherals

and Resource Domain

Control submodules

AD, RT

The XRDC Memory Region Controller

(MRC) submodule implements the

access controls for slave memories

based on the pre-programmed region

descriptor registers.

XRDC Peripheral

Access Controller

PAC

Multicore Peripherals

and Resource Domain

Control submodules

AD, RT

The XRDC Peripheral Access Controller

(PAC) implements the access controls

for slave peripherals based on the pre-

programmed domain access control

registers.

2 Clocking

2.1 Introduction

This section details the clock sources, distribution and management within the i.MX

7ULP. These functions are under joint control of the System Clock Generation (SCG)

modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)

blocks.

NOTE

References in this chapter to “Core 0” or “Processor A”

correspond to the Cortex M4 core. References in this chapter

to “Core 1” or “Processor B” correspond to the Cortex A7

core.

Clocking

i.MX 7ULP Applications Processor—Consumer, Rev. 0, 09/2020

NXP Semiconductors

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