IMX7ULPCECB2 datasheet(39/122 Pages) NXP

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13. Note that the A7 LDO can be operated in LDO-enabled mode or LDO-bypass mode. In LDO-enabled mode, the

voltage supply to the internal logic in the A7 domain is regulated by the internal LDO.

14. When using LDO-enabled mode, the voltage at the associated *_CAP ball differs from the programmed voltage

because the sense point for the LDO is on-chip.

15. To achieve minimum power consumption, VDD_PTA, VDD_PTB, VDD_PTC, VDD_PTE, and VDD_PTF must remain

powered in all modes except BAT mode.

16. VDD_PTA must be powered during a power-on reset (POR) for the SMC0 Mode register (MR) BOOTCFG field to

properly latch the boot configuration from the PTA signals (GPIO Boot mode).

17. VDD_ANA33 must be shorted to VDD_PTA at the board level.

18. VDD_PTF must be powered during a power-on reset (POR) for the SMC1 Mode register (MR) BOOTCFG field to

properly latch the boot configuration from the PTF signals (GPIO Boot mode). VDD_PTF must also remain powered

during all A7 power modes except for BAT mode.

19. VDD_DDR must remain powered while VDD18_DDR is powered.

20. The 7ULP USB PHY provides two options for reporting VBUS valid back to the USB controller:

• A programmable internal VBUS_VALID comparator (the default option), or

• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V

USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID comparator

is used, USBPHY_USB1_VBUS_DETECTn[VBUSVALID_THRESH] determines the threshold voltage for a valid

VBUS. The programmable range is 4.0V to 4.4V (default).

21. The 7ULP USB PHY provides two options for reporting VBUS valid back to the USB controller:

• A programmable internal VBUS_VALID comparator (the default option), or

• An alternate VBUS_VALID_3V detector that will report VBUS valid for voltages above 3 V.

USBPHY_USB1_VBUS_DETECTn[VBUSVALID_SEL] selects which option is used. If the VBUS_VALID_3V detector

is used, the detector voltage is not programmable.

7.1.6 Estimated maximum supply currents

This table represents the estimated maximum current on the power supply rails and

should be used for power supply selection. The data below is based on design

simulation as well as measured data. Note that some of the data in the table is based

on internal companion regulator limits and not actual use cases. Maximum currents

are higher by far than the average power consumption of typical use cases.

Table 6. Estimated maximum supply currents

Power rail

Conditions

Maximum currents

Unit

VDD_VBAT42

4.2 V

µA

VDD_PLL18

1.8 V

VDD18_IOREF + VDD_PMC18 +

VDD_PTB1

1.8 V

Use Maximum IO equation 2 + 10 mA

VDD18_DDR + VDD18_HSIC

1.8 V

VDD_ANA18 + VREFH_ANA18

1.8 V

µA

VDD_DSI18

1.8 V

0.6

VDD_USB18

1.8 V

High speed mode

VDD_PMC18_DIG0

1.8 V, CM4 200 MHz

Table continues on the next page...

System specifications

i.MX 7ULP Applications Processor—Consumer, Rev. 0, 09/2020

NXP Semiconductors

IMX7ULPCECB2 Datasheet(PDF) 39 Page - NXP Semiconductors

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