PCIMX6DP7AYM2AB datasheet(37/166 Pages) NXP

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Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

NXP Semiconductors

4.4.4

480 MHz PLL

4.4.5

MLB PLL

The MediaLB PLL is necessary in the MediaLB 6-Pin implementation to phase align the internal and

external clock edges, effectively tuning out the delay of the differential clock receiver and is also

responsible for generating the higher speed internal clock, when the internal-to-external clock ratio is

not 1:1.

4.4.6

Arm PLL

4.5

On-Chip Oscillators

4.5.1

OSC24M

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT.

The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight

forward biased-inverter implementation is used.

4.5.2

OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load

capacitors implements a low power oscillator. It also implements a power mux such that it can be powered

Table 17. 480 MHz PLL Electrical Parameters

Parameter

Value

Clock output range

480 MHz PLL output

Reference clock

24 MHz

Lock time

<383 reference cycles

Table 18. MLB PLL Electrical Parameters

Parameter

Value

Lock time

<1.5 ms

Table 19. Arm PLL Electrical Parameters

Parameter

Value

Clock output range

650 MHz~1.3 GHz

Reference clock

24 MHz

Lock time

<2250 reference cycles

PCIMX6DP7AYM2AB Datasheet(PDF) 37 Page - NXP Semiconductors

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