PCIMX6DP7AYM2AB datasheet(75/166 Pages) NXP

75 / 166 page

Electrical Characteristics

i.MX 6DualPlus/6QuadPlus Automotive Applications Processors, Rev. 3, 11/2018

NXP Semiconductors

4.12.2.2

ECSPI Slave Mode Timing

Figure 36 depicts the timing of ECSPI in slave mode and Table 48 lists the ECSPI slave mode timing

characteristics.

Figure 36. ECSPI Slave Mode Timing Diagram

Table 48. ECSPI Slave Mode Timing Parameters

Parameter

Symbol

Min

Max

Unit

CS1

ECSPIx_SCLK Cycle Time–Read

• Slow group1

• Fast group2

ECSPIx_SCLK Cycle Time–Write

1 ECSPI slow includes:

ECSPI1/DISP0_DAT22, ECSPI1/KEY_COL1, ECSPI1/CSI0_DAT6,

ECSPI2/EIM_OE, ECSPI2/DISP0_DAT17, ECSPI2/CSI0_DAT10, ECSPI3/DISP0_DAT2

2 ECSPI fast includes:

ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0

tclk

—ns

CS2

ECSPIx_SCLK High or Low Time–Read

• Slow group1

• Fast group2

ECSPIx_SCLK High or Low Time–Write

tSW

—ns

CS4

ECSPIx_SSx pulse width

tCSLH

Half ECSPIx_SCLK period

—

CS5

ECSPIx_SSx Lead Time (CS setup time)

tSCS

5—

CS6

ECSPIx_SSx Lag Time (CS hold time)

tHCS

5—

CS7

ECSPIx_MOSI Setup Time

tSmosi

4—

CS8

ECSPIx_MOSI Hold Time

tHmosi

4—

CS9

ECSPIx_MISO Propagation Delay (CLOAD =20pF)

• Slow group1

• Fast group2

tPDmiso

CS1

CS7

CS8

CS2

CS4

CS6

CS5

CS9

ECSPIx_SCLK

ECSPIx_SS_B

ECSPIx_MISO

ECSPIx_MOSI

Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be con-

nected between a single master and a single slave.

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