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ADC3641 Datasheet(PDF) 37 Page - Texas Instruments

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Part # ADC3641
Description  ADC364x 14-bit, 10-MSPS to 65-MSPS, Low-Noise, Low Power Dual Channel ADC
PDF  77 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

ADC3641 Datasheet(HTML) 37 Page - Texas Instruments

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FCLK
DA5
DA6
FCLK
DA6
2-Wire
8x Serialization
1-Wire
16x Serialization
DCLK
DCLK
A1 <15:0>
A0 <15:0>
A0
D13
A0
D11
A0
D9
A0
D7
A0
D5
A0
D3
A0
D1
A0
D12
A0
D10
A0
D8
A0
D6
A0
D4
A0
D2
A0
D0
A1
D13
A1
D11
A1
D9
A1
D7
A1
D5
A1
D3
A1
D12
A1
D10
A1
D8
A1
D6
A1
D4
A1
D2
A1
D1
A1
D0
A0
D15
A0
D14
A1
D15
A1
D14
DB5
DB6
B0
D13
B0
D11
B0
D9
B0
D7
B0
D5
B0
D3
B0
D1
B0
D12
B0
D10
B0
D8
B0
D6
B0
D4
B0
D2
B0
D0
B1
D13
B1
D11
B1
D9
B1
D7
B1
D5
B1
D3
B1
D12
B1
D10
B1
D8
B1
D6
B1
D4
B1
D2
B1
D1
B1
D0
B0
D15
B0
D14
B1
D15
B1
D14
B1 <15:0>
B0 <15:0>
DB6
1/2-Wire
(32x Serialization)
FCLK
DA6
DCLK
B0 <15:0>
A0 <15:0>
Figure 8-37. Output Data Format in Real Decimation
Table 8-6 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK
frequencies based on output resolution (R), number of serial CMOS lanes (L) and real decimation setting (M).
Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output
resolution and real decimation by 16.
Table 8-6. Serial CMOS Lane Rate Examples with Real Decimation and 16-bit Output Resolution
DECIMATION
SETTING
ADC SAMPLING
RATE
OUTPUT
RESOLUTION
# of WIRES
FCLK
DCLKIN, DCLK
DOUT
M
FS
R
L
FS / M / 2 (L = 2)
FS / M (L = 1, 1/2)
[DOUT] / 2
FS x R / L / M
16
65 MSPS
16
2
2.03125 MHz
16.25 MHz
32.5 MHz
1
4.0625 MHz
32.5 MHz
65 MHz
1/2
65 MHz
130 MHz
www.ti.com
ADC3643
SBAS886 – OCTOBER 2020
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: ADC3643



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