ADC3641 datasheet(67/77 Pages) TI

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12 Layout

12.1 Layout Guidelines

There are several critical signals which require specific care during board design:

1. Analog input and clock signals

• Traces should be as short as possible and vias should be avoided where possible to minimize impedance

discontinuities.

• Traces should be routed using loosely coupled 100-Ω differential traces.

• Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2

degradation.

2. Digital output interface

• A 20 Ω series isolation resistor should be used on each CMOS output and placed close the digital output.

This isolation resistor limits the output current into the capacitive load and thus minimizes the switching

noise inside the ADC. When driving longer distances a buffer should be used. The resistor value should

be optimized for the desired output data rate.

3. Voltage reference

• The bypass capacitor should be placed as close to the device pins as possible and connected between

VREF and REFGND – on top layer avoiding vias.

• Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be

recommended and should also be placed as close to pins as possible on top layer.

4. Power and ground connections

• Provide low resistance connection paths to all power and ground pins.

• Use power and ground planes instead of traces.

• Avoid narrow, isolated paths which increase the connection resistance.

• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power

plane.

12.2 Layout Example

The following screen shot shows the top layer of the ADC364x EVM.

• Signal and clock inputs are routed as differential signals on the top layer avoiding vias.

• Serial CMOS output interface lanes with isolation resistor and digital buffer.

• Bypass caps are close to the VREF pin on the top layer avoiding vias.

CMOS output lines with

isolation resistor and buffer

close by

Bypass caps on VREF close

to the pins

Analog inputs on

top layer (no vias)

Clock routing

without vias

Figure 12-1. Layout example: top layer of ADC364x EVM

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ADC3643

SBAS886 – OCTOBER 2020

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