Signals description

NAND01G-N

12/23

Rev1.0

2

Signals description

See Figure 1 in conjunction with Table 2, for a brief overview of the signals connected to this

device.

For extra details on the signals, refer to the NAND Flash and the LPSDRAM datasheets.

2.1

Flash memory Inputs/Outputs (I/O0-I/O7)

Input/Outputs 0 to 7 are used by the NAND Flash memory to input the selected address,

output the data during a Read operation or input a command or data during a Write

operation. The inputs are latched on the rising edge of Write Enable. I/O0-I/O7 are left

floating when the NAND Flash memory is deselected or the outputs are disabled.

2.2

Flash memory Inputs/Outputs (I/O8-I/O15)

Input/Outputs 8 to 15 are only available in x16 NAND Flash devices. They are used to output

the data during a Read operation or input data during a Write operation. Command and

Address Inputs only require I/O0 to I/O7.

The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when

the device is deselected or the outputs are disabled.

2.3

Flash memory Address Latch Enable (AL)

The Address Latch Enable activates the latching of the Address inputs in the Command

Interface of the NAND Flash memory. When AL is high, the inputs are latched on the rising

edge of Write Enable.

2.4

Flash memory Command Latch Enable (CL)

The Command Latch Enable activates the latching of the Command inputs in the Command

Interface of the NAND Flash memory. When CL is high, the inputs are latched on the rising

edge of Write Enable.

2.5

The NAND Flash memory Chip Enable input activates the memory control logic, input

busy, the device remains selected and does not go into standby mode.