NAND01G-N datasheet(15/23 Pages) STMICROELECTRONICS

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NAND01G-N

Signals description

Rev1.0

15/23

2.19

LPSDRAM Clock Input (K)

The Clock signal, K, is used to clock the Read and Write cycles on the LPSDRAM. During

normal operation, the Clock Enable pin, KE, is High, VIH. The clock signal K can be

suspended to switch the device to the Self-Refresh, Power-Down or Deep Power-Down

mode by driving KE Low, VIL.

2.20

LPSDRAM Clock Input (K)

The Clock signal, K, is only available on the DDR LPSDRAM. It is used in conjunction with

the Clock signal, K.

All LPSDRAM input signals except DQM0/DQM1, UDQS/LDQS and DQ0-DQ15 are

referred to the cross point of K rising edge and K falling edge.

2.21

LPSDRAM Clock Enable (KE)

The Clock Enable, KE, pin is used by the LPSDRAM to control the synchronizing of the

signals with Clock signal K (and K on DDR LPSDRAM). If KE is High, VIH, the next Clock

rising edge is valid. When KE is Low, VIL, the signals are no longer clocked and data Read

and Write cycles are extended. KE is also involved in switching the device to the Self-

Refresh, Power-Down and Deep Power-Down modes.

2.22

LPSDRAM Lower/Upper Data Input/Output Mask (DQM0,

DQM1)

Data Mask Enable Inputs are used to mask the Read or Write data.

2.23

Lower/Upper Data Read/Write Strobe Input/Output (LDQS,

UDQS)

LDQS and UDQS are only available on the DDR LPSDRAM. They can be either input or

output signals and act as write data strobe and read data strobe respectively. LDQS and

UDQS are the strobe signals for DQ0 to DQ7 and DQ8 to DQ15, respectively.

2.24

LPSDRAM VDDD supply voltage

VDDD provides the power supply to the internal core of the LPSDRAM. It is the main power

supply for all operations (Read and Write).

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