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CD1020 Datasheet(PDF) 40 Page - NXP Semiconductors |
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CD1020 Datasheet(HTML) 40 Page - NXP Semiconductors |
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40 / 56 page ![]() NXP Semiconductors 40 CD1020 7.10.13 Wake-up enable register SP The wake-up register defines the inputs that are allowed to wake the CD1020 from low-power mode. Programming the wake-up bit to logic [0] disables the specific input from waking the IC (Table 25). Programming the wake-up bit to logic [1] enables the specific input to wake-up with switch change of state The MCU may change or update the wake-up register via software at any time in normal mode. The Wake-up register defaults to logic [1] (wake-up enabled). If all channels (SG and SB) have the Wake-up bit disabled, the device disables the polling timer to reduce the current consumption during low-power mode. 7.10.14 Wake-up enable register SG The wake-up register defines the inputs that are allowed to wake the CD1020 from low-power mode. Programming the wake-up bit to logic [0] disables the specific input from waking the IC (Table 26). Programming the wake-up bit to logic [1] enables the specific input to wake-up with any switch change of state The MCU may change or update the wake-up register via software at any time in normal mode. The Wake-up register defaults to logic [1] (wake-up enabled). If all channels (SG and SB) have the Wake-up bit disabled, the device disables the polling timer to reduce the current consumption during low-power mode. Table 25. Wake-up enable SP register Register address R/W SPI data bits [23 – 0] [31–25] [24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0010_000 0/1 Unused Default on POR 00 000 000 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Unused 00 000 000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 111 111 MISO return word bit [23] bit [22] bits [21 – 0] 0010_000[R/W] FAULT STATUS INTflg Register Data Table 26. Wake-up enable SG register Register address R/W SPI data bits [23 – 0] [31–25] [24] bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0010_001 0/1 Unused Default on POR 0000 000 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Unused SG13 SG12 SG11 SG10 SG9 SG8 0011 111 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SG7 SG6 SG5 SG4 SG3 SG2 SG1 SG0 1111 111 1 MISO return word bit [23] bit [22] bits [21 – 0] 0010_001[R/W] FAULT STATUS INTflg Register Data |
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