CD1020 datasheet(13/56 Pages) NXP

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NXP Semiconductors

CD1020

Figure 4. Glitch filter and interrupt delay timers

SPI interface (continued)

tSCKLS

SCLK low time

• Figure 6 - 5

—

tSUS

MOSI input setup time

• Figure 6 - 6

—

tHS

MOSI input hold time

• Figure 6 - 7

—

MISO access time

• Figure 6 - 8

—

116

tDIS

MISO disable time (21)

• Figure 6 - 9

—

100

tVS

MISO output valid time

• Figure 6 - 10

—

116

tHO

MISO output hold time (no cap on MISO)

• Figure 6 - 11

—

tRO

Rise time

• Figure 6 - 12

—

(21)

tFO

Fall time

• Figure 6 - 13

—

(21)

tCSN

CS_B negated time

• Figure 6 - 14

500

—

WAKE-UP

tCSB_WAKEUP

LPM mode wake-up time triggered by edge of CS_B

—

755

1000

µs

(23)

Notes

21.

Guaranteed by characterization.

22.

AMUX settling time to be within the 10 mV offset specification. AMUXVALID is dependent on the voltage step applied on the input SGx/SPx pin or

the difference between the first and second channel selected as the multiplexed analog output. See Figure 8 for a typical AMUX access time VS

voltage step waveform.

23.

The parameter is guaranteed at VBATP = 6.0 V to 28 V.

Table 7. Dynamic electrical characteristics (continued)

TA = –40 °C to +125 °C, VDDQ = 3.1 V to 5.25 V, VBATP = 6.0 V to 28 V, unless otherwise specified. All SPI timing is performed with a

100 pF load on MISO, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Units

Notes

LPM CLK

SG_Pin

Input Glitch

filter timer

INT_B

500ns

tglitchTIMER

tINT-DLY

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