 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
Z8018010FSC Datasheet(PDF) 39 Page - Zilog, Inc. |
|
|
|||||||||||||||||||||||||||||
Z8018010FSC Datasheet(HTML) 39 Page - Zilog, Inc. |
|
|
39 / 124 page  Z 8018x Fam il y M PU Use r M anual 24 UM005001-ZMP0400 Figure 14. Instruction Timing Diagram This instruction moves the contents of a CPU register (g) to the memory location with address computed by adding a signed 8-bit displacement (d) to the contents of an index register (IX). The instruction cycle begins with the two machine cycles to read the two byte instruction Op Code as indicated by M1 Low. Next, the instruction operand (d) is fetched. Memory Write Cycle Next instruction Fetch Cycle CPU internal Operation Displacement Read Cycle 2nd Op Code Fetch Cycle 1st Op Code Fetch Cycle T1 T2 T3 T1 T3 T1 T2 T2 T3 T1 T1 T1 T1 T1 T2 T3 T2 PC+3 IX+d PC+2 PC+1 PC g (7OH –77H) (DDH) d MC1 MC2 MC3 MC4 MC5 MC6 MC7 NOTE: d = displacement g = register contents Machine Cycle WR RD MREQ Phi A0 –A19 D0 –D7 M1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
