AS5600L datasheet(17/48 Pages) AMSCO

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ams Datasheet

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[v1-12] 2020-May-14

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AS5600L − Detailed Description

Figure 18:

Data Read

Depending on the state of the R/W bit, two types of data transfer

are possible:

Data Transfer from a Master Transmitter to a Slave Receiver

The first byte transmitted by the master is the slave address,

followed by R/W = 0. Next follows a number of data bytes. The

slave returns an acknowledge bit after each received byte. If the

slave does not understand the command or data it sends a not

acknowledge (NACK). Data is transferred with the most

significant bit (MSB) first.

Data Transfer from a Slave Transmitter to a Master Receiver

The master transmits the first byte (the slave address). The slave

then returns an acknowledge bit, followed by the slave

transmitting a number of data bytes. The master returns an

acknowledge bit after all received bytes other than the last byte.

At the end of the last received byte, a NACK is returned. The

master generates all of the SCL clock periods and the START and

STOP conditions. A transfer is ended with a STOP condition or

with a repeated START condition. Because a repeated START

condition is also the beginning of the next serial transfer, the

bus is not released. Data is transferred with the most significant

bit (MSB) first.

...

SDA

SCL

Start

Condition

Stop Condition or

Repeated Start Condition

MSB

R/W

ACK

LSB

ACK

Slave Address

Repeated if more Bytes are transferred

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