AD4116BCPZ datasheet(46/59 Pages) AD

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AD4116

Data Sheet

Rev. 0 | Page 46 of 59

APPLICATIONS INFORMATION

GROUNDING AND LAYOUT

The inputs and reference inputs are differential and, therefore,

most of the voltages in the analog modulator are common-mode

voltages. The high common-mode rejection of the device removes

common-mode noise on these inputs. The analog and digital

supplies to the AD4116 are independent and separately pinned

out to minimize coupling between the analog and digital sections

of the device. The digital filter provides rejection of broadband

noise on the power supplies, except at integer multiples of the

master clock frequency.

The digital filter also removes noise from the analog inputs

and reference inputs, provided that these noise sources do not

saturate the analog modulator. As a result, the AD4116 is more

immune to noise interference than a conventional high

resolution converter. However, because the resolution of the

AD4116 is high and the noise levels from the converter are so

low, take care with regard to grounding and layout.

The PCB that houses the ADC must be designed so that the

analog and digital sections are separated and confined to

certain areas of the board. A minimum etch technique is

generally best for ground planes because it results in the best

shielding.

In any layout, the user must keep in mind the flow of currents

in the system, ensuring that the paths for all return currents are as

close as possible to the paths the currents took to reach their

destinations.

Avoid running digital lines under the device because this

couples noise onto the die and allows the analog ground plane

to run under the AD4116 to prevent noise coupling. The power

supply lines to the AD4116 must use as wide a trace as possible

to provide low impedance paths and reduce glitches on the

power supply line. Shield fast switching signals like clocks with

digital ground to prevent radiating noise to other sections of

the board and never run clock signals near the inputs. Avoid

crossover of digital and analog signals. Run traces on opposite

sides of the board at right angles to each other. This layout

reduces the effects of feedthrough on the board. A microstrip

technique is by far the best but is not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground planes, whereas signals are

placed on the solder side.

Proper decoupling is important when using high resolution ADCs.

The AD4116 has two power supply pins: AVDD and IOVDD.

The AVDD pin is referenced to AVSS, and the IOVDD pin is

referenced to DGND. Decouple AVDD with a 10 µF tantalum

capacitor in parallel with a 0.1 µF capacitor to AVSS on each

pin. Place the 0.1 µF capacitor as near as possible to the device

on each supply, ideally right up against the device. Decouple

IOVDD with a 10 µF tantalum capacitor, in parallel with a 0.1 µF

capacitor to DGND. Decouple all inputs to AVSS. If an external

reference is used, decouple the REF+ and REF− pins to AVSS.

The AD4116 also has two on-board LDO regulator outputs:

one that regulates the AVDD supply, and one that regulates the

IOVDD supply. For the REGCAPA pin, it is recommended that

1 µF and 0.1 µF capacitors to AVSS be used. Similarly, for the

REGCAPD pin, it is recommended that 1 µF and 0.1 µF

capacitors to DGND be used.

AD4116BCPZ Datasheet(PDF) 46 Page - Analog Devices

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