LTM4633 datasheet(17/36 Pages) AD

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LTM4671

Rev. B

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FREQUENCY SYNCHRONIZATION AND CLOCK IN

The power module has a phase-locked loop comprised

of an internal voltage controlled oscillator and a phase

detector. This allows all internal top MOSFET turn-on to

be locked to the rising edge of the same external clock.

The external clock frequency range must be within ±30%

around the set frequency.

A pulse detection circuit is used to detect a clock on the

MODE/CLKIN0 pin for CH0 (12A) channel, MODE/CLKIN3

pinforCH3(12A)channelandMODE/CLKIN12pinforboth

CH1andCH25Achannelstoturnonthephase-lockedloop.

The pulse width of the clock has to be at least 400ns.

The clock high level must be above 1V and clock low

level below 0.3V. During the start-up of the regulator, the

phase-locked loop function is disabled. When the module

is driven with an external clock, forced continuous mode

(CCM) is automatically enabled.

MULTICHANNEL PARALLEL OPERATION

For the application that demand more than 12A of output

current, the LTM4671 multiple regulator channels can be

easilyparalleledtorunoutofphasetoprovidemoreoutput

currentwithoutincreasinginputandoutputvoltageripples.

For the 12A channels (CH0, CH3), each channel has its

own MODE/CLKIN and CLKOUT pin. The CLKOUT signal

can be connected to the CLKIN pin of the following stage to

line up both frequency and the phase of the entire system.

Tying the PHMODE pin to INTVCC,SGNDorfloatingthepin

generates a phase difference between the clock applied on

the MODE/CLKIN pin and CLKOUT of 180° degrees, 120°

degrees, or 90° degrees respectively, which corresponds

to 2-phase, 3-phase, or 4-phase operation.

For the 5A channels (CH1, CH2), a preset built-in 180°

phase different between channel 1 and channel 2. MODE/

CLKIN12 allows both channels to be synchronized to

an external clock or the CLKOUT signal from any of the

12A channels.

Figure 2 shows a 2 + 2 and a 4-channels parallel concept

schematic for clock phasing.

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output ca-

APPLICATIONS INFORMATION

Figure 2. 2 + 2 Parallel Concept Schematic

pacitors. The RMS input ripple current is reduced by, and

the effective ripple frequency is multiplied by, the number

of phases used (assuming that the input voltage is greater

than the number of phases used times the output voltage).

The output ripple amplitude is also reduced by the number

of phases used when all of the outputs are tied together

to achieve a single high output current design.

The LTM4671 device is an inherently current mode con-

trolled device, so parallel modules will have very good

current sharing. This will balance the thermals on the

design. Please tie RUN, TRACK/SS, FB and COMP pins

of each paralleling channel together. Figure 31 shows an

example of parallel operation and pin connection.

INPUT RMS RIPPLE CURRENT CANCELLATION

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current

cancellation mathematical derivations are presented, and

a graph is displayed representing the RMS ripple current

reduction as a function of the number of interleaved

phases. Figure 3 shows this graph.

4671 F02

MODE/CLKIN0

PHMODE0

CLKOUT0

VOUT0

CH0

(0°)

LTM4671

180°

MODE/CLKIN3

PHMODE3

CLKOUT3

VOUT3

CH3

(180°)

90°

MODE/CLKIN12

VOUT1

CH1

(270°)

180°

VOUT2

CH2

(90°)

24A

10A

INTVCC0

FLOAT

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