PCF8545ATT datasheet(32/48 Pages) NXP

32 / 48 page

PCE85176AUG

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Product data sheet

Rev. 1 — 12 January 2015

32 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

13. Dynamic characteristics

[1]

Typical output duty factor: 50 % measured at the CLK output pin.

[2]

Not tested in production.

[3]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 25.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock

fclk(int)

internal clock frequency

[1] 1440

1850

2640

fclk(ext)

external clock frequency

960

2640

ffr

frame frequency

internal clock

110

external clock

110

tclk(H)

HIGH-level clock time

s

tclk(L)

LOW-level clock time

s

tPD(drv)

driver propagation delay

VLCD = 5 V

[2] --

s

I2C-bus[3]

Pin SCL

fSCL

SCL clock frequency

400

kHz

tLOW

LOW period of the SCL

clock

1.3

s

tHIGH

HIGH period of the SCL

clock

0.6

s

Pin SDA

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

Pins SCL and SDA

tBUF

bus free time between a

STOP and START

condition

1.3

s

tSU;STO

set-up time for STOP

condition

0.6

s

tHD;STA

hold time (repeated)

START condition

0.6

s

tSU;STA

set-up time for a repeated

START condition

0.6

s

rise time of both SDA and

SCL signals

fSCL = 400 kHz

0.3

s

fSCL < 125 kHz

1.0

s

fall time of both SDA and

SCL signals

0.3

s

capacitive load for each

bus line

400

tw(spike)

spike pulse width

on the I2C-bus

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