PCF8545ATT datasheet(47/48 Pages) NXP

47 / 48 page

PCE85176AUG

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Product data sheet

Rev. 1 — 12 January 2015

47 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

25. Figures

Fig 1.

Block diagram of PCE85176AUG . . . . . . . . . . . . .2

Fig 2.

Pinning diagram for PCE85176AUG (bare die) . . .3

Fig 3.

Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . . .9

Fig 4.

Relationship between LCD layout, drive mode,

display RAM filling order, and display data

transmitted over the I2C-bus . . . . . . . . . . . . . . . .10

Fig 5.

RAM writing procedure . . . . . . . . . . . . . . . . . . . . 11

Fig 6.

RAM banks in static and multiplex

driving mode 1:2 . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 7.

Bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 8.

Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . .15

Fig 9.

Example of displays suitable for PCE85176AUG 16

Fig 10. Typical system configuration . . . . . . . . . . . . . . . .16

Fig 11. Electro-optical characteristic: relative transmission

curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 12. Static drive mode waveforms . . . . . . . . . . . . . . . .20

Fig 13. Waveforms for the 1:2 multiplex drive mode

with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 14. Waveforms for the 1:2 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 15. Waveforms for the 1:3 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 16. Waveforms for the 1:4 multiplex drive mode

with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 17. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 18. Definition of START and STOP conditions. . . . . .26

Fig 19. System configuration . . . . . . . . . . . . . . . . . . . . . .27

Fig 20. Acknowledgement of the I2C-bus . . . . . . . . . . . .27

Fig 21. I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 22. Format of command byte . . . . . . . . . . . . . . . . . . .28

Fig 23. Device protection diagram . . . . . . . . . . . . . . . . . .29

Fig 24. Driver timing waveforms . . . . . . . . . . . . . . . . . . .33

Fig 25. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .33

Fig 26. Track resistances on the SDA and VSS line . . . . .34

Fig 27. Bare die outline of PCE85176AUG . . . . . . . . . . .35

Fig 28. Alignment marks of PCE85176AUG . . . . . . . . . .37

Fig 29. Tray details for PCE85176AUG . . . . . . . . . . . . . .38

Fig 30. Tray alignment for PCE85176AUG tray . . . . . . . .39

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