STM32WB55 datasheet(44/193 Pages) STMICROELECTRONICS

44 / 193 page

Functional overview

STM32WB55xx STM32WB35xx

44/193

DS11929 Rev 11

The I/Os alternate function configuration can be locked, if needed, following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.12

Direct memory access controller (DMA)

The device embeds two DMAs. Refer to Table 10 for the features implementation.

Direct memory access (DMA) is used to provide high-speed data transfer between

peripherals and memory as well as between memories. Data can be quickly moved by DMA

without any CPU action. This keeps CPU resources free for other operations.

The two DMA controllers have fourteen channels in total, a full cross matrix allows any

peripheral to be mapped on any of the available DMA channels. Each DMA has an arbiter

for handling the priority between DMA requests.

The DMA supports:



fourteen independently configurable channels (requests)



A full cross matrix between peripherals and all the DMA channels exist. There is also a

HW trigger possibility through the DMAMUX.



Priorities between requests from DMA channels are software programmable (four

levels consisting in very high, high, medium and low) or hardware in case of equality

(request 1 has priority over request 2, etc.).



Independent source and destination transfer size (byte, half word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data

size.



Support for circular buffer management.



Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error)

logically OR-ed together in a single interrupt request for each channel.



Memory-to-memory transfer.



Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral

transfers.



Access to Flash memory, SRAM, APB and AHB peripherals as source and destination.



Programmable number of data to be transferred: up to 65536.

A DMAMUX block makes it possible to route any peripheral source to any DMA channel.

3.13

Interrupts and events

3.13.1

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the



Cortex®-M4 with FPU.

Table 10. DMA implementation

DMA features

DMA1

DMA2

Number of regular channels

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