MIC2810 datasheet(16/26 Pages) MICROCHIP

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MIC2810

DS20005910B-page 16



2017 - 2022 Microchip Technology Inc. and its subsidiaries.

4.0

APPLICATION INFORMATION

The MIC2810 is a power management IC with a single

integrated step-down regulator and two low dropout

regulators. LDO1 and LDO2 are 300 mA low dropout

regulators supplied from the input voltage pins. The

step-down regulator is a 600 mA PWM power supply.

All three regulators utilize a LOWQ light load mode to

maximize battery efficiency under light load conditions.

This is achieved with a LOWQ control pin that, when

pulled low, shuts down all the biasing and drive current

for the PWM regulator, along with reducing the current

limit of the two independent LDOs. When the LOWQ

pin is pulled low, the MIC2810 draws only 30 µA of

operating current. This mode allows the output to be

regulated through the LDO output, which is capable of

providing 60 mA of output current. This method has the

advantage of producing a clean, low current, ultra-low

noise output in LOWQ mode. During LOWQ mode, the

SW node becomes high impedance, blocking current

flow. Other methods of reducing quiescent current,

such as pulse frequency modulation (PFM) or bursting

techniques create large amplitude and low frequency

ripple voltages that can be detrimental to system

operation.

When more than 60 mA is required, the LOWQ pin can

be forced high, causing the MIC2810 to enter PWM

mode. In this case, the LDO output makes a "hand-off"

to the PWM regulator with virtually no variation in

output voltage. The LDO output then turns off allowing

up to 600 mA of current to be efficiently supplied

through the PWM output to the load.

4.1

Output Capacitor

LDO1 and LDO2 outputs require a 2.2 µF ceramic

output capacitor for stability. The DC/DC switch mode

regulator also requires a 2.2 µF ceramic output

capacitor to be stable. All output capacitor values can

be increased to improve transient response, but

performance has been optimized for a 2.2 µF ceramic

on the LDOs and the DC/DC regulator. X7R/X5R

dielectric-type ceramic capacitors are recommended

because

their

temperature

performance.

X5R/X7R-type capacitors change capacitance by 15%

over their operating temperature range and are the

most stable type of ceramic capacitors. Z5U and Y5V

dielectric capacitors change value by as much as 50%

to 60% respectively over their operating temperature

ranges.

4.2

Input Capacitor

A minimum 1 µF ceramic, 4.7 µF recommended,

should be placed as close as possible to the VIN pin for

optimal bypassing. X5R or X7R dielectrics are

recommended for the input capacitor. Y5V dielectrics

lose most of their capacitance over temperature and

are therefore, not recommended. A minimum 1 µF is

recommended close to the VIN and PGND pins for high

frequency filtering. Smaller case size capacitors are

recommended due to their lower ESR and ESL. Please

refer to the PCB layout section for an example of an

appropriate circuit layout.

4.3

Inductor Selection

The MIC2810 is designed for use with a 2.2 µH

inductor. Proper selection should ensure the inductor

can handle the maximum average and peak currents

required by the load. Maximum current ratings of the

inductor are generally given in two methods;

permissible DC current and saturation current.

Permissible DC current can be rated either for a 40°C

temperature rise or a 10% to 20% loss in inductance.

Ensure that the inductor selected can handle the

maximum operating current. When saturation current is

specified, make sure that there is enough margin that

the peak current will not saturate the inductor. Peak

inductor current can be calculated as follows:

EQUATION 4-1:

4.4

POR Delay Time

The POR signal also goes low for the duration of the

delay time given by Equation 3-1 when only one of the

enable inputs (EN, EN1, EN2) transitions from low to

high, with the others being already high and the

corresponding output being in regulation. This is shown

in Figure 2-30, Figure 2-31, and Figure 2-32. At the

low-to-high transition of either enable input, the CSET

pin capacitor is discharged to ground, and the POR

delay time is restarted.

At start-up, in order to prevent a momentary HIGH

glitch of the POR signal between subsequent enable

commands, it is recommended to set the POR delay

time longer than the maximum delay expected between

the enable command signals plus the turn-on time

tTURN-ON.

For a given delay between the enable signals, an

example of correct POR delay time design is shown in

Figure 2-33 and Figure 2-34. In Figure 2-33, it can be

seen that the CSET voltage is reset to ground by

subsequent low-to-high enable signals transitions

before it reaches the VTHCSET voltage (1.25V typ.),

thus extending the duration of the POR LOW assertion

(Figure 2-34).

IPK IOUT

VOUT 1

VOUT

VIN

----------------

–













2 f



------------------------------------------------

Where:

IPK = Peak inductor current.

IOUT = Output/load current.

VIN = Input voltage.

VOUT = Output voltage.

f = Switching frequency of the PWM regulator.

L = Inductor value.

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