VSC7217 datasheet(21/36 Pages) VITESSE

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Page 21

6/14/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC7217

Multi-Gigabit Interconnect Chip

G52325-0, Rev. 3.0

Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing)

Table 10: Transmit Input AC Characteristics with TMODE = 11X

Figure 16: Transmit Serial Timing Waveforms

Table 11: Transmit Serial AC Characteristics

Parameters

Description

Min

Max

Units

Conditions

Input Skew relative to the rising

edge of

TBCn or TBCA

—

2.0

Measured between the valid data

level of the input and the 1.4V point

TBCn or TBCA, bc = Bit Clock.

Parameters

Description

Min

Max

Units

Conditions

TSDR, TSDF

TXn+/- Rise and Fall Times

—

330

Measured between 20% to

80% of the valid data level.

TLAT

Latency,

REFCLK to TX0

Latency,

TBCA to TX0

Latency,

TBCB/C/D to TX0

22bc+0.2ns

36bc+0.0ns

32bc+0.1ns

22bc+0.8ns

38bc+0.3ns

42bc+0.6ns

bc + ns

ENDEC=1 TMODE=000

ENDEC=1 TMODE=10X

ENDEC=1 TMODE=101

Serial Data Output

Total Jitter (p-p)

—

192

IEEE 802.3z Clause 38.69,

tested on a sample basis.

TDJ

Serial Data Output

Deterministic Jitter (p-p)

—

IEEE 802.3z Clause 38.69,

tested on a sample basis.

Valid

Internal Clock

(from PLL)

TBCn

(or TBCA)

Tn(7:0)

C/Dn

WSENn

TSDR, TSDF

TLAT

TXn+, TXn-

TX0

REFCLK

(or TBCn)

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