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Data Sheet

ADPA7008

BIASING ADPA7008 WITH THE HMC980LP4E

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Rev. 0 | 26 of 28

Power-Down Sequence

The power-down sequence for the HMC980LP4E is as follows:

1. Set EN = 0 V, which causes the HMC980LP4E to power-down

the VDRAIN pins and sets the VGATE = −1.5 V.

2. Set VNEG = 0 V. Note that this step is unnecessary if using the

internally generated negative voltage.

3. Set VDD = 0 V.

4. Set S0 and S1 = 0 V. The Sx pins are internally pulled up to

VDIG; therefore, this step is optional.

5. Set VDIG = 0 V.

After the HMC980LP4E bias control circuit is set up, toggle the bias

to the ADPA7008 on or off by applying 3.3 V or 0 V, respectively, to

the EN pin. When setting EN = 3.3 V, VGATE becomes less

negative as the control loop closes, and VDRAIN turns on at 5 V.

VGATE then stabilizes at the voltage required to achieve IDRAIN =

1600 mA, and the closed control loop then continues to regulate

IDRAIN at 1600 mA. When setting EN = 0 V, VGATE is set to −1.5 V,

and VDRAIN is set to 0 V.

CONSTANT DRAIN CURRENT BIASING VS.

CONSTANT GATE VOLTAGE BIASING

The HMC980LP4E uses closed-loop feedback to continuously ad-

just VGATE to maintain a constant drain current bias over dc supply

variation, temperature, and device to device variation. In addition,

constant drain current bias is the optimum method for reducing

time in calibration procedures and for maintaining consistent per-

formance over time. By comparing the constant drain current bias

with a constant gate voltage bias where the current is driven to

increase when RF power is applied, a slightly lower output P1dB is

seen with a constant drain current bias. This output P1dB is shown

in Figure 84, where the RF performance is slightly lower than the

constant gate voltage bias operation due to a lower drain current at

the high input powers as the device reaches 1 dB compression.

To increase the output P1dB performance for the constant drain

current bias toward the constant gate voltage bias performance,

increase the set current toward the IDD value this performance

reaches under the RF drive in the constant gate voltage bias

condition, as shown in Figure 84. The limit of increasing IDQ

under the constant drain current operation is set by the thermal

limitations found in Table 5 with the maximum power dissipation

specification. As IDD increase continues, the actual output P1dB

does not continue to increase indefinitely, and the power dissipation

increases. Therefore, when using constant drain current biasing,

note this exchange between power dissipation and the output P1dB

performance into consideration.

CONSTANT IDD OPERATION

TA = 25°C, VDD = 5 V, and IDQ = 1700 mA for nominal operation,

unless otherwise noted. Figure 77 to Figure 80 are biased with the

HMC980LP4E active bias controller. See the Biasing ADPA7008

with the HMC980LP4E section for biasing details.

Figure 77. Output P1dB vs. Frequency for Various Temperatures, VDD = 5 V,

Data Measured with Constant IDD

Figure 78. PSAT vs. Frequency for Various Temperatures, VDD = 5 V,

Data Measured with Constant IDD

Figure 79. Output P1dB vs. Frequency for Various Drain Currents, VDD = 5 V,

Data Measured with Constant IDD

ADPA7008AEHZ-R7 Datasheet(PDF) 26 Page - Analog Devices

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