Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

ADPD6000 Datasheet(PDF) 7 Page - Analog Devices

Part # ADPD6000
Description  Multimodal Sensor Front End
PDF  89 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADPD6000 Datasheet(HTML) 7 Page - Analog Devices

Back Button ADPD6000 Datasheet HTML 3Page - Analog Devices ADPD6000 Datasheet HTML 4Page - Analog Devices ADPD6000 Datasheet HTML 5Page - Analog Devices ADPD6000 Datasheet HTML 6Page - Analog Devices ADPD6000 Datasheet HTML 7Page - Analog Devices ADPD6000 Datasheet HTML 8Page - Analog Devices ADPD6000 Datasheet HTML 9Page - Analog Devices ADPD6000 Datasheet HTML 10Page - Analog Devices ADPD6000 Datasheet HTML 11Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 89 page
background image
Data Sheet
ADPD6000
SPECIFICATIONS
analog.com
Rev. 0 | 7 of 89
Table 2. Performance Specifications
Parameter
Test Condition/Comments
Min
Typ
Max
Unit
CALIBRATION RESISTOR
External
2
kΩ
Internal
2
kΩ
Power Consumption
1.24
mW
1 DC PSRR = 20 × log((Signal(LSB)/NUM_INT_x/NUM_REPEAT_x × 0.146 mV/LSB)/VIN (mV))
DIGITAL SPECIFICATIONS
IOVDD = 1.7 V to 3.6 V, unless otherwise noted.
Table 3. Digital Specifications
Parameter
Test Condition/Comments
Min
Typ
Max
Unit
LOGIC INPUTS
Input Voltage Level
GPIOx, MISO, MOSI, SCLK, CS
High
0.7 × IOVDD
IOVDD + 0.3
V
Low
−0.3
+0.3 × IOVDD
V
Input Current Level
All logic inputs
High
10
µA
Low
−10
µA
Input Capacitance
2
pF
LOGIC OUTPUTS
Output Voltage Level
GPIOx, MISO
High
2 mA high level output current
IOVDD – 0.5
V
Low
2 mA low level output current
0.5
V
TIMING SPECIFICATIONS
Table 4. Timing Specifications
Parameter
Symbol
Test Condition/Comments
Min
Typ
Max
Unit
SPI PORT
SCLK
Frequency
fSCLK
10
MHz
Minimum Pulse Width
High
tSCLKPWH
15
ns
Low
tSCLKPWL
15
ns
CS
Setup Time
tCSS
CS setup to SCLK rising edge
11
ns
Hold Time
tCSH
CS hold from SCLK rising edge
5
ns
Pulse Width High
tCSPWH
CS pulse width high
15
ns
MOSI
Setup Time
tMOSIS
MOSI setup to SCLK rising edge
5
ns
Hold Time
tMOSIH
MOSI hold from SCLK rising edge
5
ns
SWITCHING CHARACTERISTICS
MISO Output Delay
tMISOD
MISO valid output delay from SCLK falling edge
Register 0x0057 = 0x0050 (default)
21.5
ns
Register 0x0057 = 0x005F (maximum slew rate, maximum drive
strength for SPI)
14
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com