LTM2887 datasheet(16/30 Pages) AD

16 / 30 page

LTM2810

Rev. A

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APPLICATIONS INFORMATION

With VIN driven, the VL2 output may be adjusted from the

nominal 5V by connecting a voltage divider to the AVL2

pin as shown in Figure 5. Select the voltage divider ratio

so that the AVL2 voltage is 0.6V. The value of R1 should

be no greater than 13kΩ to minimize errors in the output

voltage caused by the adjust pin bias current and internal

voltage divider.

There is no interdependency between VCC, VL, and PVCC.

Theymaysimultaneouslyoperateatanyvoltagewithintheir

specified operating ranges and may sequence in any order.

VL is bypassed internally with a 1µF ceramic capacitor and

VL2 is bypassed internally by a 6.6µF ceramic capacitor.

Hot Plugging Safely

Caution must be exercised in applications where power is

plugged into the LTM2810’s power supplies, VCC, PVCC,

VL,orVL2duetotheintegratedceramicdecouplingcapaci-

tors. The parasitic cable inductance along with the high-Q

characteristicsofceramiccapacitorscancausesubstantial

ringing which could exceed the maximum voltage ratings

and damage the LTM2810. Refer to Application Note 88,

entitled Ceramic Input Capacitors Can Cause Overvoltage

Transients for a detailed discussion and mitigation of this

phenomenon.

Isolation Transformer

Because of the wide voltage range for VIN, there are many

optionsfortheisolationtransformerandrectifiertopology.

The selected transformer should meet the application’s

isolationrequirements,haveaminimumvolt-secondrating

greater than 0.5 • PVCC µVS and a current rating sufficient

for the LTM2810’s IVINplusanyapplicationload.Different

winding configurations and turns ratios allow the accom-

modation of different input or isolated output voltages as

illustrated by Figures 14 to 18.

Channel Timing Uncertainty

Multiplechannelsaresupportedacrosstheisolationbound-

arybyencodinganddecodingoftheinputsandoutputs.Up

to three signals in each direction are assembled as serial

packets and transferred across the isolation barrier. The

time required to transfer all three bits is 100ns maximum,

and sets the limit for how often a signal can change on the

opposite side of the barrier. Encoding and transmission is

independent for each data direction. The technique used

assignsDI1(-S)orSCL(-I)onthelogicside,andI1(-Sor-I)

on the isolated side, the highest priority such that there

is no jitter on the associated output channels, only delay.

This preemptive scheme will produce a certain amount of

uncertainty on the other isolation channels. The resulting

pulse width uncertainty on these low priority channels is

typically ±6ns, but may vary up to ±44ns if the low priority

channels are not encoded within the same high priority

serial packet.

Serial Peripheral Interface (SPI) Bus

The LTM2810-S provides an SPI compatible isolated

interface. The maximum data rate is a function of the

inherent channel propagation delays, channel to channel

pulse width uncertainty, and data direction requirements.

Channel timing is detailed in Figures 6 through 9, Table 2,

and Table 3. The SPI protocol supports four unique timing

configurations defined by the clock polarity (CPOL) and

clock phase (CPHA) summarized in Table 1.

Table 1. SPI Mode

CPOL

CPHA

DATA TO (CLOCK) RELATIONSHIP

Sample (Rising)

Setup (Falling)

Setup (Rising)

Sample (Falling)

Setup (Rising)

Setup (Falling)

Sample (Rising)

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