LTM2887 datasheet(17/30 Pages) AD

17 / 30 page

LTM2810

Rev. A

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APPLICATIONS INFORMATION

The maximum data rate for bidirectional communication

is 4MHz, based on a synchronous system, as detailed in

the timing waveforms. Slightly higher data rates may be

achieved by skewing the clock duty cycle and minimizing

the DO1 (SDO) to DI1 (SCK) setup time, however the clock

rate is still dominated by the system propagation delays. A

discussion of the critical timing paths relative to Figure 6

and Figure 7 follows. For SPI communication DI1 = SCK,

DI2 = SDI, DI3 = CS, DO1 = SDO, O1 = SCK2, O2N and

O2P = SDI2, O3 = CS2, and I1 = SDO2.

• CS to SCK (master sample SDO, 1st SDO valid)

t0 → t1 ≈ 50ns, CS to CS2 propagation delay

t1 → t1+ Isolatedslavedevicepropagation(response

time), asserts SDO2

t1 → t3 ≈ 50ns, SDO2 to SDO propagation delay

t3 → t5 Setup time for master SDO to SCK

• SDI to SCK (master data write to slave)

t2 → t4 ≈ 50ns, SDI to SDI2 propagation delay

t5 → t6 ≈ 50ns, SCK to SCK2 propagation delay

t2 → t5 ≥ 50ns,SDItoSCK,separatepacketnon-zero

setup time

t4 → t6 ≥ 50ns, SDI2 to SCK2, separate packet non-

zero setup time

• SDO to SCK (master sample SDO, subsequent SDO

valid)

Setup data transition SDI and SCK

t8 → t10 ≈ 50ns, SDI to SDI2 and SCK to SCK2

propagation delay

t10

SDO2 data transition in response to SCK2

t10 → t11 ≈ 50ns, SDO2 to SDO propagation delay

t11 → t12 Setup time for master SDO to SCK

Maximum data rate for single direction communication,

master to slave, is 8MHz, limited by the systems encod-

ing/decoding scheme or propagation delay. Timing details

for both variations of clock phase are shown in Figure 8,

Figure 9, and Table 3.

Additional requirements to insure maximum data rate are:

• CS is transmitted prior to (asynchronous) or within the

same (synchronous) data packet as SDI

• SDIandSCKsetupdatatransitionoccurwithinthesame

data packet. Referencing Figure 6, SDI can precede SCK

by up to 13ns (t7 → t8) or lag SCK by 3ns (t8 → t9)

and not violate this requirement. Similarly in Figure 8,

SDI can precede SCK by up to 13ns (t4 → t5) or lag

SCK by 3ns (t5 → t6).

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