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TAS2780 Datasheet(PDF) 42 Page - Texas Instruments |
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TAS2780 Datasheet(HTML) 42 Page - Texas Instruments |
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42 / 97 page  8.9.17 TDM_CFG3 (page=0x00 address=0x0C) [reset=10h] Bit Field Type Reset Description 7-4 RX_SLOT_R[3:0] RW 1h TDM RX Right Channel Time Slot. 3-0 RX_SLOT_L[3:0] RW 0h TDM RX Left Channel Time Slot. 8.9.18 TDM_CFG4 (page=0x00 address=0x0D) [reset=13h] Bit Field Type Reset Description 7 TX_KEEPCY RW 0h TDM and ICC TX SDOUT LSB data will be driven for full/half cycles when TX_KEEPEN is enabled 0b = Full-cycle 1b = Half-cycle 6 TX_KEEPLN RW 0h TDM and ICC TX SDOUT will hold the bus for the following when TX_KEEPEN is enabled 0b = 1 LSB cycle 1b = Always 5 TX_KEEPEN RW 0h TDM and ICC TX SDOUT bus keeper enable 0b = Disable bus keeper 1b = Enable bus keeper 4 TX_FILL RW 1h TDM and ICC TX SDOUT unused bit field fill 0b = Transmit 0 1b = Transmit Hi-Z 3-1 TX_OFFSET[2:0] RW 1h TDM TX start of frame to time slot 0 offset 0 TX_EDGE RW 1h TDM TX launch clock polarity 0b = Rising edge of SBCLK 1b = Falling edge of SBCLK 8.9.19 TDM_CFG5 (page=0x00 address=0x0E) [reset=42h] Bit Field Type Reset Description 7 Reserved R 0h Reserved 6 VSNS_TX RW 1h TDM TX voltage sense transmit 0b = Disabled 1b = Enabled 5-0 VSNS_SLOT[5:0] RW 2h TDM TX voltage sense time slot 8.9.20 TDM_CFG6 (page=0x00 address=0x0F) [reset=40h] Bit Field Type Reset Description 7 Reserved R 0h Reserved 6 ISNS_TX RW 1h TDM TX current sense transmit 0b = Disabled 1b = Enabled 5-0 ISNS_SLOT[5:0] RW 0h TDM TX current sense time slot 8.9.21 TDM_CFG7 (page=0x00 address=0x10) [reset=04h] Bit Field Type Reset Description 7 VBAT1S_SLEN RW 0h TDM TX VBAT1S time slot length 0b = Truncate to 8 bits 1b = Left justify to 16 bits 6 VBAT1S_TX RW 0h TDM TX VBAT1S transmit 0b = Disabled 1b = Enabled 5-0 VBAT1S_SLOT[5:0] RW 4h TDM TX VBAT1S time slot TAS2780 SLOSE75A – FEBRUARY 2022 – REVISED JUNE 2022 www.ti.com 42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TAS2780 |
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