DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Final
13
Version: DM9101-DS-F03
July 22, 1999
•
MII Interface (continued)
•
TX_ER (transmit coding error) transitions
synchronously with respect to TX_CLK. If TX_ER is
asserted for one or more clock periods, and TX_EN is
asserted, the PHY will emit one or more symbols that
are not part of the valid data delimiter set somewhere in
the frame being transmitted.
•
RXD (receive data) is a nibble (4 bits) of data that are
sampled by the reconciliation sublayer synchronously
with respect to RX_CLK. For each RX_CLK period
which RX_DV is asserted, RXD (3:0) are transferred
from the PHY to the MAC reconciliation sublayer.
•
RX_CLK (receive clock) output to the MAC
reconciliation sublayer is a continuous clock that
provides the timing reference for the transfer of the
RX_DV, RXD, and RX_ER signals.
•
RX_DV (receive data valid) input from the PHY to
indicate the PHY is presenting recovered and decoded
nibbles to the MAC reconciliation sublayer. To interpret
a receive frame correctly by the reconciliation sublayer,
RX_DV must encompass the frame starting no later
than the Start-of-Frame delimiter and excluding any
End-Stream delimiter.
•
RX_ER (receive error) transitions synchronously with
respect to RX_CLK. RX_ER will be asserted for 1 or
more clock periods to indicate to the reconciliation
sublayer that an error was detected somewhere in the
frame being transmitted from the PHY to the
reconciliation sublayer.
•
CRS (carrier sense) is asserted by the PHY when
either the transmit or receive medium is non-idle and
deasserted by the PHY when the transmit and receive
medium are idle. Figure 2 depicts the behavior of CRS
during 10Base-T and 100Base-TX transmission.
TXD
Preamble
SFD
Data
EFD
Preamble
SFD
Data
ESD
J/K
SSD
T/R
10Base-T
100Base-TX
TXD
CRS
CRS
IDLE
IDLE
Figure 2
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