LT3756 datasheet(21/30 Pages) AD

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LT8355-1

Rev. 0

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APPLICATIONS INFORMATION

Table 4. Conditions and Effects on FAULT, PWMTG and GATE

TYPE

CONDITION

FAULT

PWMTG

OFF

GATE

OFF

Overvoltage

VFB > 1.26V

Yes

Open LED

1.14V < VFB < 1.26V and

VISP-ISN < 25mV

Yes

Short LED

VFB < 300mV

Yes

Overcurrent

VISP-ISN > 670mV

Yes

PWM OFF

PWM < 500mV, or CTRL <

300mV, or IADJ2 < 500mV

Yes

INTVCC UVLO

INTVCC < 4.3V

Yes

Thermal Shutdown TJ > 170°C

Yes

Above Voltage

Regulation

1.26V > VFB > 1.20V

Yes

Above Current

Regulation

0.7V > VISP-ISN > 0.25V (or

set by Equation 2a/2b)

Yes

Soft-Start

To prevent a surge of current at start-up, LT8355-1 uses

an internal soft-start for each channel. This feature affects

both current limit and switching frequency. At start-up,

the system will switch at around 20% of the switching

frequency fSW with near zero current limit. As the clock

runs, both constraints relax, leading to normal operation

after around 256 switching periods. When a LED overcur-

rent occurs, or, in steady state, when short LED conditions

occur, the part immediately stops switching and enters

a cooldown period. The cooldown period lasts for at

least 2048 switching periods. At the end of the cooldown

period, the system attempts to start again, and enters

soft-start as if it had just been powered on for the first

time. Regardless of whether it is the first soft-start after

power-on or a soft-start resulting from a fault condition,

LT8355-1 will wait until the first PWM dimming pulse

arrives before beginning to power on the system. This

PWM pulse can be from an external source or from the

internal dimming PWM generator. At the arrival of the

first PWM pulse, soft-start begins, and operation contin-

ues until the system has reached steady state. Until the

system either finishes soft-start or observes the internal

control loop state nearing steady state, the PWM low logic

state is ignored and the part runs continuously.

Using the EN/UVLO Pin

The EN/UVLO pin offers two modes of operation. First,

it can be driven high (above 1.4V) or low (below 0.3V)

to act as an enable pin, turning the part on and off. In

addition to this, the pin can also be used to create an

accurate external under voltage lockout (UVLO). To use

this feature, connect the EN/UVLO pin to a resistive volt-

age divider from the VIN pin to ground. Select resistors

to program the desired minimum VIN value for operation

(see Equation 12 and Figure 7).

VIN(FALLING) = 1.25V • 1+

RUV1

RUV2

⎛

⎝⎜

⎞

⎠⎟

VIN(RISING) = 1.31V • 1+

RUV1

RUV2

⎛

⎝⎜

⎞

⎠⎟

+ 2.4µA •RUV1

(12)

Figure 7. LT8355-1 Resistor Network for Accurate UVLO.

RUV1

RUV2

VIN

LT8355-1

8355-1 F07

EN/UVLO

The EN/UVLO threshold has a hysteretic window to pre-

vent oscillating between the on and off states. When

the EN/UVLO pin falls below its falling threshold (1.25V

typical), switching stops, soft-start is reset, and if an

external PMOS is used according to instructions in the

PWM Dimming section, the load is disconnected from

the output capacitor. While the part is not enabled a cur-

rent of 2.4µA flows into the EN/UVLO pin to allow for

programmable hysteresis. Choose the value of the upper

resistor RUV1 in the EN/UVLO voltage divider such that

around 2.4µA(RUV1) provides the desired hysteresis.

When using the divider ratio, ensure that the equivalent

Thevenin resistance is at least 20k. When driving this pin,

add a 20k resistor in series.

Low Voltage (SEPIC) Start-Up

Certain power stage topologies, such as the SEPIC, may

require the part to start-up in the condition where ISP

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