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ALED8102S Datasheet(PDF) 10 Page - STMicroelectronics |
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ALED8102S Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 19 page ![]() 9 Typical application Figure 8. Typical application circuit Typical application circuit The figure above shows a typical application schematic for the ALED8102S, Cled value depends on common rail voltage connection length and driver total output current, typically it is around 47 µF; Cin is about 1 µF; current setting resistor depends on output current set (ex. with REXT = 388 Ω → IO ≈ 50 mA). The external programming resistor between R-EXT and GND should be connected as close as possible to the device. To have the proper device functionality, it is strongly suggested to follow a correct power-up sequence: VDD and VLED power supplies must be provided simultaneously or at least, VDD must be connected before VLED so to activate all internal digital control blocks earlier than LEDs power supply. If VLED anticipates driver VDD, this could result in a visible flash on connected LEDs (output stage undesired activation). Device thermal management The aim of this section is to provide some recommendation that can be useful to design the application PCB for a better power dissipation: • To decrease the device working temperature, the package exposed pad needs soldering to the board. • To improve thermal performance at least a 4-layer (e.g. 2S2P) PCB should be used. • The copper area below the package thermal pad should be as wide as possible also outside the package perimeter (using the package sides without pins) • A reasonable number of vias must connect the copper area below the package to all available PCB layers especially just below the device package (e.g. 3x3 or 4x3 vias array) but also outside the package perimeter. The smaller and closely spaced vias are, the better solution is. The best implementation is represented by copper filled vias. • On each inner layer a copper area must be provided for dissipation (wider it is better, if possible at least 4 times or more the package dimensions). A good condition is to have at least a power layer as an entire copper area (e.g. GND layer) • Traces for pin connection must be as wide as layout constrains allow • Several devices in power dissipation on the same board must be properly spaced. Figure 9 shows, once the maximum power dissipation is fixed, which ambient temperature range can be covered according to the maximum junction temperature and package thermal resistance: 37.5 °C/W for HTSSOP16 on Jedec PCB (2S2P) and conditions. With the same thermal resistance, figure 10 shows the junction temperature as a function of ambient temperature considering 1 W of power dissipation. ALED8102S Typical application DS12430 - Rev 2 page 10/19 |
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